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SPW20N60S5

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Infineon Technologies MOSFETs, TO-247-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SPW20N60S5

Infineon Technologies · MOSFETs · TO-247-3

SPW20N60S5 from Infineon Technologies, in a TO-247-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate pin; gate-source voltage limited to ±20 V DC and ±30 V AC (f >1 Hz), with threshold VGS(th) 3.5 to 5.5 V.
2 D passive Drain pin (also connected to the tab); VDS 600 V, continuous ID 20 A at TC = 25 °C, 13 A at TC = 100 °C.
3 S passive Source pin; carries the full drain current, with inverse diode continuous forward current IS of 20 A at TC = 25 °C.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package TO-247-3
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Continuous drain current, TC = 25 °C ID 20 A TC = 25 °C 1
Continuous drain current, TC = 100 °C ID 13 A TC = 100 °C 1
Pulsed drain current, tp limited by Tjmax ID puls 40 A tp limited by Tjmax 1
Avalanche energy, single pulse EAS 690 mJ ID = 10 A, VDD = 50 V 1
Avalanche energy, repetitive tAR limited by Tjmax EAR 1 ID = 20 A, VDD = 50 V 1
Avalanche current, repetitive tAR limited by Tjmax IAR 20 A tAR limited by Tjmax 1
Gate source voltage VGS -20 20 V 1
Gate source voltage AC VGS -30 30 V AC (f >1Hz) 1
Power dissipation Ptot 208 W TC = 25°C 1
Operating and storage temperature Tj , Tstg -55 150 °C 1
Drain source voltage slope dv/dt 20 V/ns VDS = 480 V, ID = 20 A, Tj = 125 °C 2
Thermal resistance, junction - case RthJC 0.6 K/W 2
Thermal resistance, junction - ambient, leaded RthJA 50 K/W leaded 2
Soldering temperature, wavesoldering Tsold 260 °C 1.6 mm (0.063 in.) from case for 10s 2
Drain-source breakdown voltage V(BR)DSS 600 V VGS=0V, ID=0.25mA 2
Gate threshold voltage VGS(th) 3.5 4.5 5.5 V ID=1000µΑ, VGS=VDS 2
Zero gate voltage drain current, Tj = 25 °C IDSS 0.5 5 µA VDS=600V, VGS=0V, Tj=25°C 2
Zero gate voltage drain current, Tj = 150 °C IDSS 250 µA VDS=600V, VGS=0V, Tj=150°C 2
Gate-source leakage current IGSS 100 nA VGS=20V, VDS=0V 2
Drain-source on-state resistance, Tj = 25 °C RDS(on) 0.16 0.19 Ω VGS=10V, ID=13A, Tj=25°C 2
Drain-source on-state resistance, Tj = 150 °C RDS(on) 0.43 Ω VGS=10V, ID=13A, Tj=150°C 2
Turn-off delay time td(off) 130 195 ns VDD=350V, VGS=0/10V, ID=20A, RG=3.6Ω 3
Fall time tf 30 45 ns VDD=350V, VGS=0/10V, ID=20A, RG=3.6Ω 3
Gate charge total Qg 79 103 nC VDD=350V, ID=20A, VGS=0 to 10V 3
Inverse diode continuous forward current IS 20 A TC=25°C 4
Inverse diode direct current, pulsed ISM 40 A 4
Inverse diode forward voltage VSD 1 1.2 V VGS=0V, IF=IS 4

CAD (KiCad official)

  • Symbol: SPW20N60S5
  • Footprint: Package_TO_SOT_THT:TO-247-3_Vertical
  • 3D model: TO-247-3 (KiCad packages3D, STEP)
  • 3D model files: spw20n60s5-etched.step / spw20n60s5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); spw20n60s5.step / spw20n60s5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (12 pp, sha256 b4af0bc9413e5350, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF