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SPD02N80C3

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Infineon Technologies MOSFETs, TO-252-2(DPAK). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SPD02N80C3

Infineon Technologies · MOSFETs · TO-252-2(DPAK)

SPD02N80C3 from Infineon Technologies, in a TO-252-2(DPAK). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate pin 1; static gate-source voltage limit is ±20 V (±30 V AC, f >1 Hz), with gate threshold 2.1 to 3.9 V.
2 D passive Drain pin 2, also connected to the tab; the device blocks 800 V drain-source and carries 2 A continuous at TC=25 °C (6 A pulsed).
3 S passive Source pin 3, the power return of the MOSFET and the anode of the body diode, which carries 2 A continuous.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package TO-252-2(DPAK)
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Continuous drain current (TC=25 °C) ID 2 A TC=25 °C 1
Continuous drain current (TC=100 °C) ID 1.2 A TC=100 °C 1
Pulsed drain current ID,pulse 6 A TC=25 °C 1
Avalanche energy, single pulse EAS 90 mJ ID=1 A, VDD=50 V 1
Avalanche energy, repetitive EAR 0.05 mJ ID=2 A, VDD=50 V 1
Avalanche current, repetitive IAR 2 A 1
MOSFET dv/dt ruggedness dv/dt 50 V/ns VDS=0…640 V 1
Gate source voltage, static VGS -20 20 V static 1
Gate source voltage, AC VGS -30 30 V AC (f >1 Hz) 1
Power dissipation Ptot 42 W TC=25 °C 1
Operating and storage temperature Tj, Tstg -55 150 °C 1
Diode pulse current IS,pulse 6 A 2
Reverse diode dv/dt dv/dt 4 V/ns ISD=ID, di/dt=400 A/µs, VDClink=400 V, Vpeak<V(BR)DSS, Tj<Tjmax 2
Thermal resistance, junction - case RthJC 3 K/W 2
Thermal resistance, junction - ambient, SMD on PCB, minimal footprint RthJA 62 K/W SMD version, device on PCB, minimal footprint 2
Thermal resistance, junction - ambient, SMD on PCB, 6 cm2 cooling area RthJA 35 K/W SMD version, device on PCB, 6 cm2 cooling area 2
Soldering temperature, reflow Tsold 260 °C MSL1 2
Drain-source breakdown voltage V(BR)DSS 800 V VGS=0 V, ID=250 µA 2
Gate threshold voltage VGS(th) 2.1 3 3.9 V VDS=VGS, ID=0.12 mA 2
Zero gate voltage drain current, Tj=25 °C IDSS 5 µA VDS=800 V, VGS=0 V, Tj=25 °C 2
Gate-source leakage current IGSS 100 nA VGS=20 V, VDS=0 V 2
Drain-source on-state resistance, Tj=25 °C RDS(on) 2.4 2.7 Ω VGS=10 V, ID=1.2 A, Tj=25 °C 2
Avalanche breakdown voltage V(BR)DS 870 V VGS=0 V, ID=2 A 2
Zero gate voltage drain current, Tj=150 °C IDSS 25 µA VDS=800 V, VGS=0 V, Tj=150 °C 2
Drain-source on-state resistance, Tj=150 °C RDS(on) 6.5 Ω VGS=10 V, ID=1.2 A, Tj=150 °C 2
Gate resistance RG 1.2 Ω f=1 MHz, open drain 2
Input capacitance Ciss 290 pF VGS=0 V, VDS=100 V, f=1 MHz 3
Output capacitance Coss 13 pF VGS=0 V, VDS=100 V, f=1 MHz 3
Effective output capacitance, energy related Co(er) 11 pF VGS=0 V, VDS=0 V to 480 V 3
Effective output capacitance, time related Co(tr) 26 pF VGS=0 V, VDS=0 V to 480 V 3
Turn-on delay time td(on) 25 ns VDD=400 V, VGS=0/10 V, ID=2 A, RG=47 Ω, Tj=25 °C 3
Rise time tr 15 ns VDD=400 V, VGS=0/10 V, ID=2 A, RG=47 Ω, Tj=25 °C 3
Turn-off delay time td(off) 72 ns VDD=400 V, VGS=0/10 V, ID=2 A, RG=47 Ω, Tj=25 °C 3
Fall time tf 18 ns VDD=400 V, VGS=0/10 V, ID=2 A, RG=47 Ω, Tj=25 °C 3
Gate to source charge Qgs 1.5 nC VDD=640 V, ID=2 A, VGS=0 to 10 V 3
Gate to drain charge Qgd 6 nC VDD=640 V, ID=2 A, VGS=0 to 10 V 3
Gate charge total Qg 12 16 nC VDD=640 V, ID=2 A, VGS=0 to 10 V 3
Gate plateau voltage Vplateau 5.5 V VDD=640 V, ID=2 A, VGS=0 to 10 V 3
Diode forward voltage VSD 1 1.2 V VGS=0 V, IF=IS=2 A, Tj=25 °C 3
Reverse recovery time trr 520 ns VR=400 V, IF=IS=2 A, diF/dt=100 A/µs 3
Reverse recovery charge Qrr 2 µC VR=400 V, IF=IS=2 A, diF/dt=100 A/µs 3
Peak reverse recovery current Irrm 6 A VR=400 V, IF=IS=2 A, diF/dt=100 A/µs 3

CAD (KiCad official)

  • Symbol: SPD02N80C3
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252-2(DPAK) (KiCad packages3D, STEP)
  • 3D model files: spd02n80c3-etched.step / spd02n80c3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); spd02n80c3.step / spd02n80c3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (10 pp, sha256 38b298ea0dc4ea31, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF