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SPC56EL60L5CBFSR

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersspc56el60l5cbfsrfactory-2.0.0extractor-text
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Symbol & Footprint

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Contents

README

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SPC56EL60L5CBFSR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

SPC56EL60L5CBFSR from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NMI input Non-maskable interrupt input (input only) with de-glitching filter; pad contains a weak pull-up.
2 A[6] bidirectional GPIO[6] by default (ALT0); alternates DSPI_1 SCK (ALT1) and EIRQ[6] input.
3 D[1] bidirectional GPIO[49] by default; alternates eTimer_1 ETC[2], CTU_0 EXT_TGR, and FlexRay CA_RX input.
4 F[4] bidirectional GPIO[84] by default; ALT2 is NPC MDO[3] (Nexus trace output).
5 F[5] bidirectional GPIO[85] by default; ALT2 is NPC MDO[2] (Nexus trace output).
6 VDD_HV_IO power_in 3.3 V input/output supply; recommended operating range 3.0 V to 3.63 V.
7 VSS_HV_IO power_in 3.3 V input/output ground (0 V).
8 F[6] bidirectional GPIO[86] by default; ALT2 is NPC MDO[1] (Nexus trace output).
9 MDO0 output Nexus Message Data Output line, output only, configured for Fast pad speed.
10 A[7] bidirectional GPIO[7] by default; ALT1 DSPI_1 SOUT and EIRQ[7] input.
11 C[4] bidirectional GPIO[36] by default; alternates DSPI_0 CS0, FlexPWM_0 X[1], SSCM DEBUG[4], and EIRQ[22] input.
12 A[8] bidirectional GPIO[8] by default; DSPI_1 SIN input and EIRQ[8] input.
13 C[5] bidirectional GPIO[37] by default; alternates DSPI_0 SCK, SSCM DEBUG[5], FlexPWM_0 FAULT[3] input, and EIRQ[23] input.
14 A[5] bidirectional GPIO[5] by default; alternates DSPI_1 CS0, eTimer_1 ETC[5], DSPI_0 CS7, and EIRQ[5] input.
15 C[7] bidirectional GPIO[39] by default; alternates FlexPWM_0 A[1], SSCM DEBUG[7], and DSPI_0 SIN input.
16 VDD_HV_REG_0 power_in 3.3 V voltage regulator supply; recommended operating range 3.0 V to 3.63 V.
17 VSS_LV_COR power_in Core regulator ground; decoupling capacitor must connect to the nearest VDD_LV_COR pin.
18 VDD_LV_COR power_in Core logic supply decoupling pin; decoupling capacitor must connect to the nearest VSS_LV_COR pin.
19 F[7] bidirectional GPIO[87] by default; ALT2 is NPC MCKO (Nexus clock output).
20 F[8] bidirectional GPIO[88] by default; ALT2 is NPC MSEO[1] (Nexus message start/end output).
21 VDD_HV_IO power_in 3.3 V input/output supply; recommended operating range 3.0 V to 3.63 V.
22 VSS_HV_IO power_in 3.3 V input/output ground (0 V).
23 F[9] bidirectional GPIO[89] by default; ALT2 is NPC MSEO[0] (Nexus output).
24 F[10] bidirectional GPIO[90] by default; ALT2 is NPC EVTO (Nexus event output).
25 F[11] bidirectional GPIO[91] by default; NPC EVTI (Nexus event input) is the function on this pin.
26 D[9] bidirectional GPIO[57] by default; alternates FlexPWM_0 X[0] and LINFlexD_1 TXD.
27 VDD_HV_OSC power_in Crystal oscillator amplifier supply; recommended operating range 3.0 V to 3.63 V.
28 VSS_HV_OSC power_in Crystal oscillator amplifier ground (0 V).
29 XTAL input Input for the oscillator amplifier circuit and internal clock generator (input only).
30 EXTAL bidirectional Oscillator amplifier output in crystal mode and input in external clock mode.
31 RESET bidirectional Bidirectional reset with Schmitt-trigger and noise filter, open-drain output that must be terminated by an external 1 kOhm resistor; output valid only after the 3.3 V supply is stable.
32 D[8] bidirectional GPIO[56] by default; alternates DSPI_1 CS2, eTimer_1 ETC[4], DSPI_0 CS5, and FlexPWM_0 FAULT[3] input.
33 D[5] bidirectional GPIO[53] by default; alternates DSPI_0 CS3 and FlexPWM_0 FAULT[2] input.
34 D[6] bidirectional GPIO[54] by default; alternates DSPI_0 CS2, FlexPWM_0 X[3], and FlexPWM_0 FAULT[1] input.
35 VSS_LV_PLL0_PLL1 power_in 1.2 V FMPLL ground; decoupling capacitor connects between this pin and VDD_LV_PLL0_PLL1.
36 VDD_LV_PLL0_PLL1 power_in 1.2 V FMPLL supply decoupling pin; capacitor connects between this pin and VSS_LV_PLL0_PLL1.
37 D[7] bidirectional GPIO[55] by default; alternates DSPI_1 CS3, DSPI_0 CS4, and SWG analog output.
38 FCCU_F[0] bidirectional FCCU fault pin F[0], used to report failures to the external system via a configurable output.
39 VDD_LV_COR power_in Core logic supply decoupling pin; capacitor connects to the nearest VSS_LV_COR pin.
40 VSS_LV_COR power_in Core regulator ground; capacitor connects to the nearest VDD_LV_COR pin.
41 C[1] input GPIO[33] input-only pad; ADC_0 analog input AN[2].
42 E[4] input GPIO[68] input-only pad; ADC_0 analog input AN[7].
43 B[7] input GPIO[23] input-only pad; LINFlexD_0 RXD input and ADC_0 analog input AN[0].
44 E[5] input GPIO[69] input-only pad; ADC_0 analog input AN[8].
45 C[2] input GPIO[34] input-only pad; ADC_0 analog input AN[3].
46 E[6] input GPIO[70] input-only pad; ADC_0 analog input AN[4].
47 B[8] input GPIO[24] input-only pad; ADC_0 analog input AN[1] and eTimer_0 ETC[5] input.
48 E[7] input GPIO[71] input-only pad; ADC_0 analog input AN[6].
49 E[2] input GPIO[66] input-only pad; ADC_0 analog input AN[5].
50 VDD_HV_ADR0 power_in ADC_0 high reference voltage; 4.5 V to 5.5 V or 3.0 V to 3.63 V per the recommended operating conditions.
51 VSS_HV_ADR0 power_in ADC_0 low reference voltage and ground (0 V).
52 B[9] input GPIO[25] input-only pad; shared analog input AN[11] for ADC_0/ADC_1.
53 B[10] input GPIO[26] input-only pad; shared analog input AN[12] for ADC_0/ADC_1.
54 B[11] input GPIO[27] input-only pad; shared analog input AN[13] for ADC_0/ADC_1.
55 B[12] input GPIO[28] input-only pad; shared analog input AN[14] for ADC_0/ADC_1.
56 VDD_HV_ADR1 power_in ADC_1 high reference voltage; 4.5 V to 5.5 V or 3.0 V to 3.63 V per the recommended operating conditions.
57 VSS_HV_ADR1 power_in ADC_1 low reference voltage and ground (0 V).
58 VDD_HV_ADV power_in ADC supply voltage for ADC_0 and ADC_1; 3.3 V nominal, absolute maximum 4.5 V.
59 VSS_HV_ADV power_in ADC ground for ADC_0 and ADC_1 (0 V).
60 B[13] input GPIO[29] input-only pad; LINFlexD_1 RXD input and ADC_1 analog input AN[0].
61 E[9] input GPIO[73] input-only pad; ADC_1 analog input AN[7].
62 B[15] input GPIO[31] input-only pad; EIRQ[20] input and ADC_1 analog input AN[2].
63 E[10] input GPIO[74] input-only pad; ADC_1 analog input AN[8].
64 B[14] input GPIO[30] input-only pad; eTimer_0 ETC[4] input, EIRQ[19] input, and ADC_1 analog input AN[1].
65 E[11] input GPIO[75] input-only pad; ADC_1 analog input AN[4].
66 C[0] input GPIO[32] input-only pad; ADC_1 analog input AN[3].
67 E[12] input GPIO[76] input-only pad; ADC_1 analog input AN[6].
68 E[0] input GPIO[64] input-only pad; ADC_1 analog input AN[5].
69 BCTRL passive Voltage regulator external NPN ballast transistor base control pin.
70 VDD_LV_COR power_in Core logic supply decoupling pin; capacitor connects to the nearest VSS_LV_COR pin.
71 VSS_LV_COR power_in Core regulator ground; capacitor connects to the nearest VDD_LV_COR pin.
72 VDD_HV_PMU power_in Voltage regulator supply; recommended operating range 3.0 V to 3.63 V.
73 A[0] bidirectional GPIO[0] by default; alternates eTimer_0 ETC[0], DSPI_2 SCK, and EIRQ[0] input.
74 A[1] bidirectional GPIO[1] by default; alternates eTimer_0 ETC[1], DSPI_2 SOUT, and EIRQ[1] input.
75 G[11] bidirectional GPIO[107] by default; alternates FlexRay DBG3 and FlexPWM_0 FAULT[3] input.
76 D[10] bidirectional GPIO[58] by default; alternates FlexPWM_0 A[0] and eTimer_0 ETC[0] input.
77 G[10] bidirectional GPIO[106] by default; alternates FlexRay DBG2, DSPI_2 CS3, and FlexPWM_0 FAULT[2] input.
78 D[11] bidirectional GPIO[59] by default; alternates FlexPWM_0 B[0] and eTimer_0 ETC[1] input.
79 G[9] bidirectional GPIO[105] by default; alternates FlexRay DBG1, DSPI_1 CS1, FlexPWM_0 FAULT[1] input, and EIRQ[29] input.
80 C[11] bidirectional GPIO[43] by default; alternates eTimer_0 ETC[4] and DSPI_2 CS2.
81 G[8] bidirectional GPIO[104] by default; alternates FlexRay DBG0, DSPI_0 CS1, FlexPWM_0 FAULT[0] input, and EIRQ[21] input.
82 C[12] bidirectional GPIO[44] by default; alternates eTimer_0 ETC[5] and DSPI_2 CS3.
83 G[7] bidirectional GPIO[103] by default; alternate FlexPWM_0 B[3].
84 A[2] bidirectional GPIO[2] by default with pull-down during reset; alternates eTimer_0 ETC[2], FlexPWM_0 A[3], DSPI_2 SIN input, MC_RGM ABS[0], and EIRQ[2] input.
85 G[5] bidirectional GPIO[101] by default; alternates FlexPWM_0 X[3] and DSPI_2 CS3.
86 B[5] bidirectional GPIO[21] by default with weak pull-up; JTAGC TDI input.
87 TMS input JTAG state machine control input with weak pull-up.
88 TCK input JTAG clock input with weak pull-up.
89 B[4] bidirectional GPIO[20] by default; default function after reset is JTAGC TDO (ALT1), Fast pad speed.
90 VSS_HV_IO power_in 3.3 V input/output ground (0 V).
91 VDD_HV_IO power_in 3.3 V input/output supply; recommended operating range 3.0 V to 3.63 V.
92 A[3] bidirectional GPIO[3] by default with pull-down during reset; alternates eTimer_0 ETC[3], DSPI_2 CS0, FlexPWM_0 B[3], MC_RGM ABS[2], and EIRQ[3] input.
93 VDD_LV_COR power_in Core logic supply decoupling pin; capacitor connects to the nearest VSS_LV_COR pin.
94 VSS_LV_COR power_in Core regulator ground; capacitor connects to the nearest VDD_LV_COR pin.
95 VDD_HV_REG_1 power_in 3.3 V voltage regulator supply; recommended operating range 3.0 V to 3.63 V.
96 VSS_HV_FLA power_in Flash memory ground (0 V).
97 VDD_HV_FLA power_in 3.3 V flash supply; recommended operating range 3.0 V to 3.63 V.
98 G[6] bidirectional GPIO[102] by default; alternate FlexPWM_0 A[3].
99 D[12] bidirectional GPIO[60] by default; alternates FlexPWM_0 X[1] and LINFlexD_1 RXD input.
100 G[4] bidirectional GPIO[100] by default; alternates FlexPWM_0 B[2] and eTimer_0 ETC[5] input.
101 C[13] bidirectional GPIO[45] by default; alternates eTimer_1 ETC[1], CTU_0 EXT_IN input, and FlexPWM_0 EXT_SYNC input.
102 G[2] bidirectional GPIO[98] by default; alternates FlexPWM_0 X[2] and DSPI_1 CS1.
103 C[14] bidirectional GPIO[46] by default; alternates eTimer_1 ETC[2] and CTU_0 EXT_TGR.
104 G[3] bidirectional GPIO[99] by default; alternates FlexPWM_0 A[2] and eTimer_0 ETC[4] input.
105 D[14] bidirectional GPIO[62] by default; alternates FlexPWM_0 B[1] and eTimer_0 ETC[3] input.
106 F[12] bidirectional GPIO[92] by default; alternates eTimer_1 ETC[3] and EIRQ[30] input.
107 VPP_TEST input Test pin for testing purposes only; must be tied to ground (VSS) in normal operating mode.
108 A[4] bidirectional GPIO[4] by default with pull-down during reset; alternates eTimer_1 ETC[0], DSPI_2 CS1, eTimer_0 ETC[4], MC_RGM FAB, and EIRQ[4] input.
109 B[0] bidirectional GPIO[16] by default; alternates FlexCAN_0 TXD, eTimer_1 ETC[2], SSCM DEBUG[0], and EIRQ[15] input.
110 B[1] bidirectional GPIO[17] by default; alternates eTimer_1 ETC[3], SSCM DEBUG[1], FlexCAN_0/FlexCAN_1 RXD input, and EIRQ[16] input.
111 C[10] bidirectional GPIO[42] by default; alternates DSPI_2 CS2, FlexPWM_0 A[3], and FlexPWM_0 FAULT[1] input.
112 F[13] bidirectional GPIO[93] by default; alternates eTimer_1 ETC[4] and EIRQ[31] input.
113 F[15] bidirectional GPIO[95] by default; LINFlexD_1 RXD input.
114 B[2] bidirectional GPIO[18] by default; alternates LINFlexD_0 TXD, SSCM DEBUG[2], and EIRQ[17] input.
115 F[14] bidirectional GPIO[94] by default; alternate LINFlexD_1 TXD.
116 B[3] bidirectional GPIO[19] by default; alternates SSCM DEBUG[3] and LINFlexD_0 RXD input.
117 E[13] bidirectional GPIO[77] by default; alternates eTimer_0 ETC[5], DSPI_2 CS3, and EIRQ[25] input.
118 A[10] bidirectional GPIO[10] by default; alternates DSPI_2 CS0, FlexPWM_0 B[0], FlexPWM_0 X[2], and EIRQ[9] input.
119 E[14] bidirectional GPIO[78] by default; alternates eTimer_1 ETC[5] and EIRQ[26] input.
120 A[11] bidirectional GPIO[11] by default; alternates DSPI_2 SCK, FlexPWM_0 A[0], FlexPWM_0 A[2], and EIRQ[10] input.
121 E[15] bidirectional GPIO[79] by default; alternates DSPI_0 CS1 and EIRQ[27] input.
122 A[12] bidirectional GPIO[12] by default; alternates DSPI_2 SOUT, FlexPWM_0 A[2], FlexPWM_0 B[2], and EIRQ[11] input.
123 JCOMP input JTAG compliance select input with weak pull-down.
124 C[15] bidirectional GPIO[47] by default; alternates FlexRay CA_TR_EN, eTimer_1 ETC[0], FlexPWM_0 A[1], CTU_0 EXT_IN input, and FlexPWM_0 EXT_SYNC input.
125 D[0] bidirectional GPIO[48] by default; alternates FlexRay CA_TX, eTimer_1 ETC[1], and FlexPWM_0 B[1].
126 VDD_HV_IO power_in 3.3 V input/output supply; recommended operating range 3.0 V to 3.63 V.
127 VSS_HV_IO power_in 3.3 V input/output ground (0 V).
128 D[3] bidirectional GPIO[51] by default; alternates FlexRay CB_TX, eTimer_1 ETC[4], and FlexPWM_0 A[3].
129 D[4] bidirectional GPIO[52] by default; alternates FlexRay CB_TR_EN, eTimer_1 ETC[5], and FlexPWM_0 B[3].
130 VDD_HV_REG_2 power_in 3.3 V voltage regulator supply; recommended operating range 3.0 V to 3.63 V.
131 VDD_LV_COR power_in Core logic supply decoupling pin; capacitor connects to the nearest VSS_LV_COR pin.
132 VSS_LV_COR power_in Core regulator ground; capacitor connects to the nearest VDD_LV_COR pin.
133 F[0] bidirectional GPIO[80] by default; alternates FlexPWM_0 A[1], eTimer_0 ETC[2], and EIRQ[28] input.
134 A[9] bidirectional GPIO[9] by default with pull-down during reset; alternates DSPI_2 CS1, FlexPWM_0 B[3], and FlexPWM_0 FAULT[0] input.
135 VDD_LV_COR power_in Core logic supply decoupling pin; capacitor connects to the nearest VSS_LV_COR pin.
136 A[13] bidirectional GPIO[13] by default; alternates FlexPWM_0 B[2], DSPI_2 SIN input, FlexPWM_0 FAULT[0] input, and EIRQ[12] input.
137 VSS_LV_COR power_in Core regulator ground; capacitor connects to the nearest VDD_LV_COR pin.
138 B[6] bidirectional GPIO[22] by default, Fast pad speed; alternates MC_CGM clk_out, DSPI_2 CS2, and EIRQ[18] input.
139 F[3] bidirectional GPIO[83] by default; alternate DSPI_0 CS6.
140 D[2] bidirectional GPIO[50] by default; alternates eTimer_1 ETC[3], FlexPWM_0 X[3], and FlexRay CB_RX input.
141 FCCU_F[1] bidirectional FCCU fault pin F[1], used to report failures to the external system via a configurable output.
142 C[6] bidirectional GPIO[38] by default; alternates DSPI_0 SOUT, FlexPWM_0 B[1], SSCM DEBUG[6], and EIRQ[24] input.
143 A[14] bidirectional GPIO[14] by default; alternates FlexCAN_1 TXD, eTimer_1 ETC[4], and EIRQ[13] input.
144 A[15] bidirectional GPIO[15] by default; alternates eTimer_1 ETC[5], FlexCAN_1 RXD input, FlexCAN_0 RXD input, and EIRQ[14] input.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

CAD (KiCad official)

  • Symbol: SPC56EL60L5CBFSR
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: spc56el60l5cbfsr-etched.step / spc56el60l5cbfsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); spc56el60l5cbfsr.step / spc56el60l5cbfsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (165 pp, sha256 29051d3f52371acd, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF