component
SPC564A80L7CFAR
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-176(24x24). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSPC564A80L7CFAR
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-176(24x24)
SPC564A80L7CFAR from STMicroelectronics, in a LQFP-176(24x24). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AN[18] | input | Single-ended analog input AN18 to the eQADC, powered from the 5 V VDDA analog segment. |
| 2 | AN[17] | input | Single-ended analog input AN17 to the eQADC, powered from the 5 V VDDA analog segment. |
| 3 | AN[16] | input | Single-ended analog input AN16 to the eQADC, powered from the 5 V VDDA analog segment. |
| 4 | AN[11]/ANZ | input | Single-ended analog input AN11, also usable as multiplexed analog input ANZ, on the 5 V VDDA segment. |
| 5 | AN[9]/ANX | input | Single-ended analog input AN9, also usable as external multiplexed analog input ANX, on the 5 V VDDA segment. |
| 6 | VDDA | power_in | eQADC high reference and analog supply, specified at 5 V with reference to VSSA. |
| 7 | VSSA | power_in | eQADC analog ground and low reference voltage. |
| 8 | AN[39] | input | Single-ended analog input AN39 to the eQADC, powered from the 5 V VDDA analog segment. |
| 9 | AN[8]/ANW | input | Single-ended analog input AN8, also usable as multiplexed analog input ANW, on the 5 V VDDA segment. |
| 10 | VDDREG | power_in | Voltage regulator supply input at 5 V, with the datasheet maximum given as 5.25 V. |
| 11 | VRCCTL | output | Voltage regulator control output used to drive the external core regulator circuit. |
| 12 | VSTBY | power_in | Power supply for standby SRAM, 0.95 to 1.2 V in unregulated mode or 2.0 to 5.5 V in regulated mode. |
| 13 | VRC33 | power_out | Internal 3.3 V regulator output; the datasheet says do not use VRC33 to drive external circuits. |
| 14 | MCKO | output | Nexus message clock output, a free-running clock for timing MDO and MSEO, on the VRC33 fast pad. |
| 15 | VSS | power_in | Ground reference for the device. |
| 16 | NC | unconnected | No-connect pin; leave unconnected, since connection to any circuit or voltage may cause unpredictable behavior or damage. |
| 17 | MDO[0] | output | Nexus trace message data output 0, which also indicates crystal oscillator stability after power-on reset and must not be connected directly to a supply or ground. |
| 18 | MDO[1] | output | Nexus trace message data output 1 on the VRC33 fast pad; must not be connected directly to a supply or ground. |
| 19 | MDO[2] | output | Nexus trace message data output 2 on the VRC33 fast pad; must not be connected directly to a supply or ground. |
| 20 | MDO[3] | output | Nexus trace message data output 3 on the VRC33 fast pad; must not be connected directly to a supply or ground. |
| 21 | ETPUA31/DSPI_C_PCS[4]/ETPUA13_O/GPIO[145] | bidirectional | eTPU A channel 31, also DSPI C peripheral chip select 4 or GPIO145, on a medium VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 22 | ETPUA30/DSPI_C_PCS[3]/ETPUA11_O/GPIO[144] | bidirectional | eTPU A channel 30, also DSPI C peripheral chip select 3 or GPIO144, on a medium VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 23 | ETPUA29/DSPI_C_PCS[2]/RCH5_C/GPIO[143] | bidirectional | eTPU A channel 29, also DSPI C peripheral chip select 2, reaction channel 5C or GPIO143, on a medium VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 24 | ETPUA28/DSPI_C_PCS[1]/RCH5_B/GPIO[142] | bidirectional | eTPU A channel 28, also DSPI C peripheral chip select 1, reaction channel 5B or GPIO142, on a medium VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 25 | ETPUA27/IRQ[15]/DSPI_C_SOUT_LVDS+/DSPI_B_SOUT/GPIO[141] | bidirectional | eTPU A channel 27, also external interrupt IRQ15, LVDS positive DSPI C data out or GPIO141, on a slow+LVDS VDDEH1 segment at 3.3 to 5.0 V. |
| 26 | ETPUA26/IRQ[14]/DSPI_C_SOUT_LVDS-/GPIO[140] | bidirectional | eTPU A channel 26, also external interrupt IRQ14, LVDS negative DSPI C data out or GPIO140, on a slow+LVDS VDDEH1 segment at 3.3 to 5.0 V. |
| 27 | ETPUA25/IRQ[13]/DSPI_C_SCK_LVDS+/GPIO[139] | bidirectional | eTPU A channel 25, also external interrupt IRQ13, LVDS positive DSPI C clock or GPIO139, on a medium+LVDS VDDEH1 segment at 3.3 to 5.0 V. |
| 28 | ETPUA24/IRQ[12]/DSPI_C_SCK_LVDS-/GPIO[138] | bidirectional | eTPU A channel 24, also external interrupt IRQ12, LVDS negative DSPI C clock or GPIO138, on a slow+LVDS VDDEH1 segment at 3.3 to 5.0 V. |
| 29 | VSS | power_in | Ground reference for the device. |
| 30 | ETPUA23/IRQ[11]/ETPUA21_O/FR_A_TX_EN/GPIO[137] | bidirectional | eTPU A channel 23, also external interrupt IRQ11, FlexRay channel A TX enable or GPIO137, on a slow VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 31 | VDDEH1A | power_in | I/O supply input for the VDDEH1 segment at 3.3 to 5.0 V; shorted internally to VDDEH1B and VDDEH1AB. |
| 32 | ETPUA22/IRQ[10]/ETPUA17_O/GPIO[136] | bidirectional | eTPU A channel 22, also external interrupt IRQ10 or GPIO136, on a slow VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 33 | VDD | power_in | 1.2 V core supply for input or decoupling; absolute maximum 1.32 V. |
| 34 | ETPUA21/IRQ[9]/RCH0_C/FR_A_RX/GPIO[135] | bidirectional | eTPU A channel 21, also external interrupt IRQ9, reaction channel 0C, FlexRay channel A RX or GPIO135, on a slow VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 35 | ETPUA20/IRQ[8]/RCH0_B/FR_A_TX/GPIO[134] | bidirectional | eTPU A channel 20, also external interrupt IRQ8, reaction channel 0B, FlexRay channel A TX or GPIO134, on a slow VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 36 | ETPUA19/DSPI_D_PCS[4]/RCH5_A/GPIO[133] | bidirectional | eTPU A channel 19, also DSPI D peripheral chip select 4, reaction channel 5A or GPIO133, on a slow VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 37 | ETPUA18/DSPI_D_PCS[3]/RCH4_A/GPIO[132] | bidirectional | eTPU A channel 18, also DSPI D peripheral chip select 3, reaction channel 4A or GPIO132, on a medium VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 38 | ETPUA17/DSPI_D_PCS[2]/RCH3_A/GPIO[131] | bidirectional | eTPU A channel 17, also DSPI D peripheral chip select 2, reaction channel 3A or GPIO131, on a medium VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 39 | ETPUA16/DSPI_D_PCS[1]/RCH2_A/GPIO[130] | bidirectional | eTPU A channel 16, also DSPI D peripheral chip select 1, reaction channel 2A or GPIO130, on a medium VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 40 | ETPUA15/DSPI_B_PCS[5]/RCH1_A/GPIO[129] | bidirectional | eTPU A channel 15, also DSPI B peripheral chip select 5, reaction channel 1A or GPIO129, on a medium VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 41 | VDDEH1B | power_in | I/O supply input for the VDDEH1 segment at 3.3 to 5.0 V; shorted internally to VDDEH1A and VDDEH1AB. |
| 42 | ETPUA14/DSPI_B_PCS[4]/ETPUA9_O/RCH0_A/GPIO[128] | bidirectional | eTPU A channel 14, also DSPI B peripheral chip select 4, eTPU A channel 9 output-only, reaction channel 0A or GPIO128, on a medium VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 43 | VSS | power_in | Ground reference for the device. |
| 44 | NIC | unconnected | Pin marked NIC has no internal connection. |
| 45 | VDD | power_in | 1.2 V core supply for input or decoupling; absolute maximum 1.32 V. |
| 46 | ETPUA13/DSPI_B_PCS[3]/GPIO[127] | bidirectional | eTPU A channel 13, also DSPI B peripheral chip select 3 or GPIO127, on a medium VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 47 | ETPUA12/DSPI_B_PCS[1]/RCH4_C/GPIO[126] | bidirectional | eTPU A channel 12, also DSPI B peripheral chip select 1, reaction channel 4C or GPIO126, on a medium VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 48 | ETPUA11/ETPUA23_O/RCH4_B/GPIO[125] | bidirectional | eTPU A channel 11, also eTPU A channel 23 output-only, reaction channel 4B or GPIO125, on a slow VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 49 | ETPUA10/ETPUA22_O/RCH1_C/GPIO[124] | bidirectional | eTPU A channel 10, also eTPU A channel 22 output-only, reaction channel 1C or GPIO124, on a slow VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 50 | ETPUA9/ETPUA21_O/RCH1_B/GPIO[123] | bidirectional | eTPU A channel 9, also eTPU A channel 21 output-only, reaction channel 1B or GPIO123, on a slow VDDEH1 I/O segment at 3.3 to 5.0 V. |
| 51 | ETPUA8/ETPUA20_O/DSPI_B_SOUT_LVDS+/GPIO[122] | bidirectional | eTPU A channel 8, also eTPU A channel 20 output-only, LVDS positive DSPI B data out or GPIO122, on a slow+LVDS VDDEH4 segment at 3.3 to 5.0 V. |
| 52 | ETPUA7/ETPUA19_O/DSPI_B_SOUT_LVDS-/ETPUA6_O/GPIO[121] | bidirectional | eTPU A channel 7, also eTPU A channel 19 and 6 output-only, LVDS negative DSPI B data out or GPIO121, on a slow+LVDS VDDEH4 segment at 3.3 to 5.0 V. |
| 53 | ETPUA6/ETPUA18_O/DSPI_B_SCK_LVDS+/FR_B_RX/GPIO[120] | bidirectional | eTPU A channel 6, also eTPU A channel 18 output-only, LVDS positive DSPI B clock, FlexRay channel B RX or GPIO120, on a medium+LVDS VDDEH4 segment at 3.3 to 5.0 V. |
| 54 | ETPUA5/ETPUA17_O/DSPI_B_SCK_LVDS-/FR_B_TX_EN/GPIO[119] | bidirectional | eTPU A channel 5, also eTPU A channel 17 output-only, LVDS negative DSPI B clock, FlexRay channel B TX enable or GPIO119, on a slow+LVDS VDDEH4 segment at 3.3 to 5.0 V. |
| 55 | VDDEH4A | power_in | I/O supply input for the VDDEH4 segment at 3.3 to 5.0 V; shorted internally to the other VDDEH4 segments. |
| 56 | ETPUA4/ETPUA16_O/FR_B_TX/GPIO[118] | bidirectional | eTPU A channel 4, also eTPU A channel 16 output-only, FlexRay channel B TX or GPIO118, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 57 | VSS | power_in | Ground reference for the device. |
| 58 | ETPUA3/ETPUA15_O/GPIO[117] | bidirectional | eTPU A channel 3, also eTPU A channel 15 output-only or GPIO117, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 59 | ETPUA2/ETPUA14_O/GPIO[116] | bidirectional | eTPU A channel 2, also eTPU A channel 14 output-only or GPIO116, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 60 | ETPUA1/ETPUA13_O/GPIO[115] | bidirectional | eTPU A channel 1, also eTPU A channel 13 output-only or GPIO115, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 61 | ETPUA0/ETPUA12_O/ETPUA19_O/GPIO[114] | bidirectional | eTPU A channel 0, also eTPU A channels 12 and 19 output-only or GPIO114, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 62 | VDD | power_in | 1.2 V core supply for input or decoupling; absolute maximum 1.32 V. |
| 63 | EMIOS0/ETPUA0_O/ETPUA25_O/GPIO[179] | bidirectional | eMIOS channel 0, also eTPU A channels 0 and 25 output-only or GPIO179, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 64 | EMIOS1/ETPUA1_O/GPIO[180] | bidirectional | eMIOS channel 1, also eTPU A channel 1 output-only or GPIO180, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 65 | EMIOS2/ETPUA2_O/RCH2_B/GPIO[181] | bidirectional | eMIOS channel 2, also eTPU A channel 2 output-only, reaction channel 2B or GPIO181, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 66 | EMIOS3/ETPUA3_O/GPIO[182] | bidirectional | eMIOS channel 3, also eTPU A channel 3 output-only or GPIO182, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 67 | EMIOS4/ETPUA4_O/RCH2_C/GPIO[183] | bidirectional | eMIOS channel 4, also eTPU A channel 4 output-only, reaction channel 2C or GPIO183, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 68 | EMIOS6/ETPUA6_O/GPIO[185] | bidirectional | eMIOS channel 6, also eTPU A channel 6 output-only or GPIO185, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 69 | EMIOS7/ETPUA7_O/GPIO[186] | bidirectional | eMIOS channel 7, also eTPU A channel 7 output-only or GPIO186, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 70 | EMIOS8/ETPUA8_O/SCI_B_TX/GPIO[187] | bidirectional | eMIOS channel 8, also eTPU A channel 8 output-only, eSCI B TX or GPIO187, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 71 | EMIOS9/ETPUA9_O/SCI_B_RX/GPIO[188] | bidirectional | eMIOS channel 9, also eTPU A channel 9 output-only, eSCI B RX or GPIO188, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 72 | VSS | power_in | Ground reference for the device. |
| 73 | EMIOS10/DSPI_D_PCS[3]/RCH3_B/GPIO[189] | bidirectional | eMIOS channel 10, also DSPI D peripheral chip select 3, reaction channel 3B or GPIO189, on a medium VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 74 | VDDEH4B | power_in | I/O supply input for the VDDEH4 segment at 3.3 to 5.0 V; shorted internally to the other VDDEH4 segments. |
| 75 | EMIOS11/DSPI_D_PCS[4]/RCH3_C/GPIO[190] | bidirectional | eMIOS channel 11, also DSPI D peripheral chip select 4, reaction channel 3C or GPIO190, on a medium VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 76 | EMIOS12/DSPI_C_SOUT/ETPUA27_O/GPIO[191] | bidirectional | eMIOS channel 12, also DSPI C data out, eTPU A channel 27 output-only or GPIO191, on a medium VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 77 | EMIOS13/DSPI_D_SOUT/GPIO[192] | bidirectional | eMIOS channel 13, also DSPI D data out or GPIO192, on a medium VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 78 | EMIOS14/IRQ[0]/ETPUA29_O/GPIO[193] | bidirectional | eMIOS channel 14, also external interrupt IRQ0, eTPU A channel 29 output-only or GPIO193, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 79 | EMIOS15/IRQ[1]/GPIO[194] | bidirectional | eMIOS channel 15, also external interrupt IRQ1 or GPIO194, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 80 | EMIOS23/GPIO[202] | bidirectional | eMIOS channel 23 or GPIO202, on a slow VDDEH4 I/O segment at 3.3 to 5.0 V. |
| 81 | CAN_A_TX/SCI_A_TX/GPIO[83] | bidirectional | FlexCAN A transmit, also eSCI A TX or GPIO83, on a slow VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 82 | CAN_A_RX/SCI_A_RX/GPIO[84] | bidirectional | FlexCAN A receive, also eSCI A RX or GPIO84, on a slow VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 83 | PLLREF/IRQ[4]/ETRIG[2]/GPIO[208] | bidirectional | FMPLL mode selection at reset (0 selects external reference clock, 1 selects XTAL oscillator mode), also external interrupt IRQ4, eQADC trigger 2 or GPIO208, on a slow VDDEH6 segment at 3.3 to 5.0 V. |
| 84 | SCI_B_RX/DSPI_D_PCS[5]/GPIO[92] | bidirectional | eSCI B receive, also DSPI D peripheral chip select 5 or GPIO92, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 85 | BOOTCFG1/IRQ[3]/ETRIG[3]/GPIO[212] | bidirectional | Boot configuration input BOOTCFG1 sampled during RSTOUT assertion, also external interrupt IRQ3, eQADC trigger 3 or GPIO212, on a slow VDDEH6 segment at 3.3 to 5.0 V. |
| 86 | WKPCFG/NMI/DSPI_B_SOUT/GPIO[213] | bidirectional | Weak pull configuration input sampled at reset (0 selects pulldown, 1 selects pullup on eTPU and eMIOS pins), also NMI, DSPI B data out or GPIO213, on a medium VDDEH6 segment at 3.3 to 5.0 V. |
| 87 | SCI_B_TX/DSPI_D_PCS[1]/GPIO[91] | bidirectional | eSCI B transmit, also DSPI D peripheral chip select 1 or GPIO91, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 88 | CAN_B_TX/DSPI_C_PCS[3]/SCI_C_TX/GPIO[85] | bidirectional | FlexCAN B transmit, also DSPI C peripheral chip select 3, eSCI C TX or GPIO85, on a slow VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 89 | CAN_B_RX/DSPI_C_PCS[4]/SCI_C_RX/GPIO[86] | bidirectional | FlexCAN B receive, also DSPI C peripheral chip select 4, eSCI C RX or GPIO86, on a slow VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 90 | VSS | power_in | Ground reference for the device. |
| 91 | VDDPLL | power_in | FMPLL supply voltage at 1.2 V. |
| 92 | EXTAL/EXTCLK | input | Crystal oscillator input or external clock input, on the VDDEH6 analog segment at 3.3 to 5.0 V. |
| 93 | XTAL | output | Crystal oscillator output on the VDDEH6 analog segment at 3.3 to 5.0 V. |
| 94 | VSS | power_in | Ground reference for the device. |
| 95 | VDDEH6A | power_in | I/O supply input for the VDDEH6 segment at 3.3 to 5.0 V; shorted internally to the other VDDEH6 segments. |
| 96 | VSS | power_in | Ground reference; the datasheet states this pin should be tied low. |
| 97 | RESET | input | Active-low reset input on the VDDEH6 segment; an internal reset asserts only if RESET is low for 10 clock cycles. |
| 98 | CAN_C_RX/DSPI_D_PCS[4]/GPIO[88] | bidirectional | FlexCAN C receive, also DSPI D peripheral chip select 4 or GPIO88, on a slow VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 99 | SCI_A_RX/EMIOS15/GPIO[90] | bidirectional | eSCI A receive, also eMIOS channel 15 or GPIO90, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 100 | SCI_A_TX/EMIOS13/GPIO[89] | bidirectional | eSCI A transmit, also eMIOS channel 13 or GPIO89, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 101 | CAN_C_TX/DSPI_D_PCS[3]/GPIO[87] | bidirectional | FlexCAN C transmit, also DSPI D peripheral chip select 3 or GPIO87, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 102 | RSTOUT | output | Active-low push-pull reset output driven low for all internal and external reset sources, on the VDDEH6 segment. |
| 103 | VDD | power_in | 1.2 V core supply for input or decoupling; absolute maximum 1.32 V. |
| 104 | DSPI_B_PCS[5]/DSPI_C_PCS[0]/GPIO[110] | bidirectional | DSPI B peripheral chip select 5, also DSPI C peripheral chip select 0 or GPIO110, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 105 | DSPI_B_PCS[4]/DSPI_C_SCK/GPIO[109] | bidirectional | DSPI B peripheral chip select 4, also DSPI C clock or GPIO109, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 106 | DSPI_B_SCK/DSPI_C_PCS[1]/GPIO[102] | bidirectional | DSPI B clock, also DSPI C peripheral chip select 1 or GPIO102, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 107 | DSPI_B_PCS[2]/DSPI_C_SOUT/GPIO[107] | bidirectional | DSPI B peripheral chip select 2, also DSPI C data out or GPIO107, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 108 | VSS | power_in | Ground reference for the device. |
| 109 | DSPI_B_PCS[1]/DSPI_D_PCS[0]/GPIO[106] | bidirectional | DSPI B peripheral chip select 1, also DSPI D peripheral chip select 0 or GPIO106, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 110 | VDDEH6B | power_in | I/O supply input for the VDDEH6 segment at 3.3 to 5.0 V; shorted internally to the other VDDEH6 segments. |
| 111 | DSPI_B_PCS[0]/DSPI_D_PCS[2]/GPIO[105] | bidirectional | DSPI B peripheral chip select 0, also DSPI D peripheral chip select 2 or GPIO105, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 112 | DSPI_B_SIN/DSPI_C_PCS[2]/GPIO[103] | bidirectional | DSPI B data in, also DSPI C peripheral chip select 2 or GPIO103, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 113 | DSPI_B_SOUT/DSPI_C_PCS[5]/GPIO[104] | bidirectional | DSPI B data out, also DSPI C peripheral chip select 5 or GPIO104, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 114 | DSPI_B_PCS[3]/DSPI_C_SIN/GPIO[108] | bidirectional | DSPI B peripheral chip select 3, also DSPI C data in or GPIO108, on a medium VDDEH6 I/O segment at 3.3 to 5.0 V. |
| 115 | VSS | power_in | Ground reference for the device. |
| 116 | EVTI | input | Nexus event input, read on the negation of RESET to enable or disable the Nexus debug port, on a VDDEH7 pad at 3.3 to 5.0 V. |
| 117 | MSEO[1] | output | Nexus message start/end output indicating the start or end of a variable-length MDO message, on a VDDEH7 pad. |
| 118 | MSEO[0] | output | Nexus message start/end output indicating the start or end of a variable-length MDO message, on a VDDEH7 pad. |
| 119 | NC | unconnected | No-connect pin according to the figure listing; leave unconnected. |
| 120 | EVTO | output | Nexus event output providing timing for a single watchpoint or breakpoint occurrence; datasheet recommends clamping to 3.3 V for 3.3 V tools. |
| 121 | JCOMP | input | JTAG TAP controller enable input on a VDDEH7 MultiV pad (low swing when JTAG selected). |
| 122 | GPIO[219] | bidirectional | General-purpose I/O 219 on a VDDEH7 MultiV pad; the same PCR also controls MCKO. |
| 123 | TDO | output | JTAG test data output on a VDDEH7 MultiV pad. |
| 124 | MDO[11]/ETPUA29_O/GPIO[82] | bidirectional | Nexus message data output 11, also eTPU A channel 29 output-only or GPIO82, on a VDDEH7 MultiV pad; do not connect directly to a supply or ground. |
| 125 | VDDEH7A | power_in | I/O supply input for the VDDEH7 segment at 3.3 to 5.0 V; VDDEH7 cannot be below 4.5 V in low-swing mode. |
| 126 | MDO[4]/ETPUA2_O/GPIO[75] | bidirectional | Nexus message data output 4, also eTPU A channel 2 output-only or GPIO75, on a VDDEH7 MultiV pad; do not connect directly to a supply or ground. |
| 127 | VSS | power_in | Ground reference for the device. |
| 128 | TCK | input | JTAG test clock input for the on-chip test logic on a VDDEH7 MultiV pad. |
| 129 | MDO[5]/ETPUA4_O/GPIO[76] | bidirectional | Nexus message data output 5, also eTPU A channel 4 output-only or GPIO76, on a VDDEH7 MultiV pad; do not connect directly to a supply or ground. |
| 130 | TDI | input | JTAG serial test instruction and data input on a VDDEH7 MultiV pad. |
| 131 | TMS | input | JTAG test mode select input on a VDDEH7 MultiV pad. |
| 132 | VDD | power_in | 1.2 V core supply for input or decoupling; absolute maximum 1.32 V. |
| 133 | VSS | power_in | Ground reference for the device. |
| 134 | MDO[10]/ETPUA27_O/GPIO[81] | bidirectional | Nexus message data output 10, also eTPU A channel 27 output-only or GPIO81, on a VDDEH7 MultiV pad; do not connect directly to a supply or ground. |
| 135 | MDO[6]/ETPUA13_O/GPIO[77] | bidirectional | Nexus message data output 6, also eTPU A channel 13 output-only or GPIO77, on a VDDEH7 MultiV pad; do not connect directly to a supply or ground. |
| 136 | MDO[7]/ETPUA19_O/GPIO[78] | bidirectional | Nexus message data output 7, also eTPU A channel 19 output-only or GPIO78, on a VDDEH7 MultiV pad; do not connect directly to a supply or ground. |
| 137 | MDO[8]/ETPUA21_O/GPIO[79] | bidirectional | Nexus message data output 8, also eTPU A channel 21 output-only or GPIO79, on a VDDEH7 MultiV pad; do not connect directly to a supply or ground. |
| 138 | VDDEH7B | power_in | I/O supply input for the VDDEH7 segment at 3.3 to 5.0 V. |
| 139 | MDO[9]/ETPUA25_O/GPIO[80] | bidirectional | Nexus message data output 9, also eTPU A channel 25 output-only or GPIO80, on a VDDEH7 MultiV pad; do not connect directly to a supply or ground. |
| 140 | VSS | power_in | Ground reference for the device. |
| 141 | CS[2]/DSPI_D_SCK/GPIO[98] | bidirectional | Chip select output CS2 (external bus), also DSPI D clock or GPIO98, on a medium VDDEH7 I/O segment at 3.3 to 5.0 V. |
| 142 | CS[3]/DSPI_D_SIN/GPIO[99] | bidirectional | Chip select output CS3 (external bus), also DSPI D data in or GPIO99, on a medium VDDEH7 I/O segment at 3.3 to 5.0 V. |
| 143 | GPIO[206]/ETRIG0 | bidirectional | General-purpose I/O 206, also eQADC trigger input ETRIG0 (must be configured as input when used as ETRIG), on a slow VDDEH7 segment at 3.3 to 5.0 V. |
| 144 | GPIO[207]/ETRIG1 | bidirectional | General-purpose I/O 207, also eQADC trigger input ETRIG1 (must be configured as input when used as ETRIG), on a slow VDDEH7 segment at 3.3 to 5.0 V. |
| 145 | AN[15]/FCK/ETPUA29_O | bidirectional | Single-ended analog input AN15, also eQADC free-running clock FCK or eTPU A channel 29 output-only, on a medium VDDEH7 segment at 3.3 to 5.0 V; tie VDDEH7 to VDDA when analog function is used. |
| 146 | AN[14]/SDI/MA[2]/ETPUA27_O | bidirectional | Single-ended analog input AN14, also eQADC serial data in SDI, mux address MA2 or eTPU A channel 27 output-only, on a medium VDDEH7 segment at 3.3 to 5.0 V; tie VDDEH7 to VDDA when analog function is used. |
| 147 | AN[13]/SDO/MA[1]/ETPUA21_O | bidirectional | Single-ended analog input AN13, also eQADC serial data out SDO, mux address MA1 or eTPU A channel 21 output-only, on a medium VDDEH7 segment at 3.3 to 5.0 V; tie VDDEH7 to VDDA when analog function is used. |
| 148 | AN[12]/SDS/MA[0]/ETPUA19_O | bidirectional | Single-ended analog input AN12, also eQADC serial data select SDS, mux address MA0 or eTPU A channel 19 output-only, on a medium VDDEH7 segment at 3.3 to 5.0 V; tie VDDEH7 to VDDA when analog function is used. |
| 149 | VDD | power_in | 1.2 V core supply for input or decoupling; absolute maximum 1.32 V. |
| 150 | AN[35] | input | Single-ended analog input AN35 to the eQADC, on the 5 V VDDA segment. |
| 151 | AN[34] | input | Single-ended analog input AN34 to the eQADC, on the 5 V VDDA segment. |
| 152 | AN[33] | input | Single-ended analog input AN33 to the eQADC, on the 5 V VDDA segment. |
| 153 | AN[32] | input | Single-ended analog input AN32 to the eQADC, on the 5 V VDDA segment. |
| 154 | AN[31] | input | Single-ended analog input AN31 to the eQADC, on the 5 V VDDA segment. |
| 155 | AN[30] | input | Single-ended analog input AN30 to the eQADC, on the 5 V VDDA segment. |
| 156 | AN[28] | input | Single-ended analog input AN28 to the eQADC, on the 5 V VDDA segment. |
| 157 | AN[27] | input | Single-ended analog input AN27 to the eQADC, on the 5 V VDDA segment. |
| 158 | AN[25] | input | Single-ended analog input AN25 to the eQADC, on the 5 V VDDA segment. |
| 159 | AN[24] | input | Single-ended analog input AN24 to the eQADC, on the 5 V VDDA segment. |
| 160 | AN[23] | input | Single-ended analog input AN23 to the eQADC, on the 5 V VDDA segment. |
| 161 | AN[22] | input | Single-ended analog input AN22 to the eQADC, on the 5 V VDDA segment. |
| 162 | VRL | power_in | eQADC voltage reference low input. |
| 163 | VRH | power_in | eQADC voltage reference high input, referenced to VRL. |
| 164 | REFBYPC | passive | eQADC reference bypass capacitor input. |
| 165 | AN[7]/DAN3- | input | Single-ended analog input AN7, also negative terminal of differential input DAN3, on the 5 V VDDA segment. |
| 166 | AN[6]/DAN3+ | input | Single-ended analog input AN6, also positive terminal of differential input DAN3, on the 5 V VDDA segment. |
| 167 | AN[5]/DAN2- | input | Single-ended analog input AN5, also negative terminal of differential input DAN2, on the 5 V VDDA segment. |
| 168 | AN[4]/DAN2+ | input | Single-ended analog input AN4, also positive terminal of differential input DAN2, on the 5 V VDDA segment. |
| 169 | AN[3]/DAN1- | input | Single-ended analog input AN3, also negative terminal of differential input DAN1, on the 5 V VDDA segment. |
| 170 | AN[2]/DAN1+ | input | Single-ended analog input AN2, also positive terminal of differential input DAN1, on the 5 V VDDA segment. |
| 171 | AN[1]/DAN0- | input | Single-ended analog input AN1, also negative terminal of differential input DAN0, on the 5 V VDDA segment. |
| 172 | AN[0]/DAN0+ | input | Single-ended analog input AN0, also positive terminal of differential input DAN0, on the 5 V VDDA segment. |
| 173 | AN[21] | input | Single-ended analog input AN21 to the eQADC, on the 5 V VDDA segment. |
| 174 | AN[36] | input | Single-ended analog input AN36 to the eQADC, on the 5 V VDDA segment. |
| 175 | AN[37] | input | Single-ended analog input AN37 to the eQADC, on the 5 V VDDA segment. |
| 176 | VDD | power_in | 1.2 V core supply for input or decoupling; absolute maximum 1.32 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-176(24x24) |
| Category | Embedded Processors & Controllers |
| Pins | 176 |
CAD (KiCad official)
- Symbol:
SPC564A80L7CFAR - Footprint:
Package_QFP:LQFP-176_24x24mm_P0.5mm - 3D model: LQFP-176(24x24) (KiCad packages3D, STEP)
- 3D model files:
spc564a80l7cfar-etched.step/spc564a80l7cfar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);spc564a80l7cfar.step/spc564a80l7cfar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (157 pp, sha256
e98dae7c8ca8a9c5, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).