component
SPC563M64L5COAY
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+180@@ -0,0 +1,180 @@+# SPC563M64L5COAY++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)++SPC563M64L5COAY from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AN[18] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 2 | AN[17] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 3 | AN[16] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 4 | AN[11] | input | Single-ended analog input AN[11], also the ANZ external multiplexed analog input, powered from VDDA. |+| 5 | AN[9] | input | Single-ended analog input AN[9], also the ANX external multiplexed analog input, powered from VDDA. |+| 6 | VDDA | power_in | Analog power input for the eQADC, nominal 5.0 V. |+| 7 | VSSA | power_in | Analog ground input for the eQADC. |+| 8 | AN[39] | input | Multiplexed single-ended analog input AN[39]/AN[10]/ANY, powered from VDDA. |+| 9 | AN[38] | input | Multiplexed single-ended analog input AN[38]/AN[8]/ANW, powered from VDDA. |+| 10 | VDDREG | power_in | Voltage regulator supply input, nominal 5.0 V. |+| 11 | VRCCTL | output | Voltage regulator control output that drives the external pass transistor for the 1.2 V supply. |+| 12 | VSTBY | power_in | Power supply for the standby RAM. |+| 13 | VRC33 | passive | 3.3 V voltage regulator bypass capacitor connection. |+| 14 | eTPU_A[31] | bidirectional | eTPU_A channel 31, alternates DSPI_C_PCS[4], eTPU_A[13] and GPIO[145]; medium pad powered from VDDEH1. |+| 15 | eTPU_A[30] | bidirectional | eTPU_A channel 30, alternates DSPI_C_PCS[3], eTPU_A[11] and GPIO[144]; medium pad powered from VDDEH1. |+| 16 | eTPU_A[29] | bidirectional | eTPU_A channel 29 (input and output), alternates DSPI_C_PCS[2] and GPIO[143]; medium pad. |+| 17 | eTPU_A[28] | bidirectional | eTPU_A channel 28 (input and output), alternates DSPI_C_PCS[1] and GPIO[142]; medium pad. |+| 18 | eTPU_A[27] | bidirectional | eTPU_A channel 27 (input and output), alternates IRQ[15], DSPI_C_SOUT_LVDS+, DSPI_B_SOUT and GPIO[141]; slow pad. |+| 19 | eTPU_A[26] | bidirectional | eTPU_A channel 26 (input and output), alternates IRQ[14], DSPI_C_SOUT_LVDS- and GPIO[140]; slow pad. |+| 20 | eTPU_A[25] | bidirectional | eTPU_A channel 25 (input and output), alternates IRQ[13], DSPI_C_SCK_LVDS+ and GPIO[139]; medium pad. |+| 21 | eTPU_A[24] | bidirectional | eTPU_A channel 24 (input and output), alternates IRQ[12], DSPI_C_SCK_LVDS- and GPIO[138]; slow pad. |+| 22 | VSS | power_in | Ground. |+| 23 | eTPU_A[23] | bidirectional | eTPU_A channel 23, alternates IRQ[11], eTPU_A[21] and GPIO[137]; slow pad. |+| 24 | VDDEH1A | power_in | I/O supply input for the VDDEH1 segment, 3.3 V to 5.0 V; shorted with VDDEH1B in production packages. |+| 25 | eTPU_A[22] | bidirectional | eTPU_A channel 22, alternates IRQ[10], eTPU_A[17] and GPIO[136]; slow pad. |+| 26 | VDD | power_in | Internal logic supply input, 1.2 V. |+| 27 | eTPU_A[21] | bidirectional | eTPU_A channel 21, alternates IRQ[9] and GPIO[135]; slow pad. |+| 28 | eTPU_A[20] | bidirectional | eTPU_A channel 20, alternates IRQ[8] and GPIO[134]; slow pad. |+| 29 | eTPU_A[19] | bidirectional | eTPU_A channel 19, alternate GPIO[133]; slow pad. |+| 30 | eTPU_A[18] | bidirectional | eTPU_A channel 18, alternate GPIO[132]; slow pad. |+| 31 | eTPU_A[17] | bidirectional | eTPU_A channel 17, alternate GPIO[131]; slow pad. |+| 32 | eTPU_A[16] | bidirectional | eTPU_A channel 16, alternate GPIO[130]; slow pad. |+| 33 | eTPU_A[15] | bidirectional | eTPU_A channel 15, alternates DSPI_B_PCS[5] and GPIO[129]; medium pad. |+| 34 | VDDEH1B | power_in | I/O supply input for the VDDEH1 segment, 3.3 V to 5.0 V; shorted with VDDEH1A in production packages. |+| 35 | eTPU_A[14] | bidirectional | eTPU_A channel 14, alternates DSPI_B_PCS[4], eTPU_A[9] and GPIO[128]; medium pad. |+| 36 | VSS | power_in | Ground. |+| 37 | eTPU_A[13] | bidirectional | eTPU_A channel 13, alternates DSPI_B_PCS[3] and GPIO[127]; medium pad. |+| 38 | eTPU_A[12] | bidirectional | eTPU_A channel 12, alternates DSPI_B_PCS[1] and GPIO[126]; medium pad. |+| 39 | eTPU_A[11] | bidirectional | eTPU_A channel 11, alternates eTPU_A[23] and GPIO[125]; slow pad. |+| 40 | eTPU_A[10] | bidirectional | eTPU_A channel 10, alternates eTPU_A[22] and GPIO[124]; slow pad. |+| 41 | eTPU_A[9] | bidirectional | eTPU_A channel 9, alternates eTPU_A[21] and GPIO[123]; slow pad. |+| 42 | eTPU_A[8] | bidirectional | eTPU_A channel 8, alternates eTPU_A[20], DSPI_B_SOUT_LVDS+ and GPIO[122]; slow pad. |+| 43 | eTPU_A[7] | bidirectional | eTPU_A channel 7, alternates eTPU_A[19], DSPI_B_SOUT_LVDS-, eTPU_A[6] and GPIO[121]; slow pad. |+| 44 | eTPU_A[6] | bidirectional | eTPU_A channel 6, alternates eTPU_A[18], DSPI_B_SCK_LVDS+ and GPIO[120]; medium pad. |+| 45 | eTPU_A[5] | bidirectional | eTPU_A channel 5, alternates eTPU_A[17], DSPI_B_SCK_LVDS- and GPIO[119]; slow pad. |+| 46 | VDDEH1B | power_in | I/O supply input for the VDDEH1 segment, 3.3 V to 5.0 V; shorted with VDDEH1A in production packages. |+| 47 | eTPU_A[4] | bidirectional | eTPU_A channel 4, alternates eTPU_A[16] and GPIO[118]; slow pad. |+| 48 | VSS | power_in | Ground. |+| 49 | eTPU_A[3] | bidirectional | eTPU_A channel 3, alternates eTPU_A[15] and GPIO[117]; slow pad. |+| 50 | eTPU_A[2] | bidirectional | eTPU_A channel 2, alternates eTPU_A[14] and GPIO[116]; slow pad. |+| 51 | eTPU_A[1] | bidirectional | eTPU_A channel 1, alternates eTPU_A[13] and GPIO[115]; slow pad. |+| 52 | eTPU_A[0] | bidirectional | eTPU_A channel 0, alternates eTPU_A[12], eTPU_A[19] and GPIO[114]; slow pad. |+| 53 | VDD | power_in | Internal logic supply input, 1.2 V. |+| 54 | eMIOS[0] | bidirectional | eMIOS channel 0, alternates eTPU_A[0], eTPU_A[25] (output only) and GPIO[179]; slow pad. |+| 55 | eMIOS[2] | bidirectional | eMIOS channel 2, alternates eTPU_A[2] and GPIO[181]; slow pad. |+| 56 | eMIOS[4] | bidirectional | eMIOS channel 4, alternates eTPU_A[4] and GPIO[183]; slow pad on VDDEH6a. |+| 57 | eMIOS[8] | bidirectional | eMIOS channel 8, alternates eTPU_A[8] (output only), SCI_B_TX and GPIO[187]; slow pad. |+| 58 | eMIOS[9] | bidirectional | eMIOS channel 9, alternates eTPU_A[9] (output only), SCI_B_RX and GPIO[188]; slow pad. |+| 59 | VSS | power_in | Ground. |+| 60 | eMIOS[10] | bidirectional | eMIOS channel 10, alternate GPIO[189]; slow pad. |+| 61 | VDDEH6A | power_in | I/O supply input for the VDDEH6 segment, 3.3 V to 5.0 V; shorted with VDDEH6B in production packages. |+| 62 | eMIOS[11] | bidirectional | eMIOS channel 11, alternate GPIO[190]; slow pad. |+| 63 | eMIOS[12] | bidirectional | eMIOS channel 12, alternates DSPI_C_SOUT, eTPU_A[27] and GPIO[191]; medium pad. |+| 64 | eMIOS[14] | bidirectional | eMIOS channel 14, alternates IRQ[0], eTPU_A[29] and GPIO[193]; slow pad. |+| 65 | eMIOS[23] | bidirectional | eMIOS channel 23, alternate GPIO[202]; slow pad. |+| 66 | CAN_A_TX | bidirectional | CAN_A transmit output, alternates SCI_A_TX and GPIO[83]; slow pad, weak pull-up after reset. |+| 67 | CAN_A_RX | bidirectional | CAN_A receive input, alternates SCI_A_RX and GPIO[84]; slow pad, weak pull-up after reset. |+| 68 | PLLREF | input | FMPLL mode selection at reset (PLLREF=0 selects external reference mode), alternates IRQ[4], ETRIG[2] and GPIO[208]. |+| 69 | SCI_B_RX | bidirectional | eSCI_B receive input, alternate GPIO[92]; slow pad, weak pull-up after reset. |+| 70 | BOOTCFG1 | input | Boot configuration input sampled during RSTOUT assertion (0 = internal flash boot, 1 = FlexCAN/eSCI boot), alternates IRQ[3], ETRIG[3] and GPIO[212]. |+| 71 | WKPCFG | input | Weak pull configuration input latched at reset to select pull-up or pull-down on eTPU and eMIOS pins, alternates NMI, DSPI_B_SOUT and GPIO[213]. |+| 72 | SCI_B_TX | bidirectional | eSCI_B transmit output, alternate GPIO[91]; slow pad, weak pull-up after reset. |+| 73 | VSS | power_in | Ground. |+| 74 | VDDPLL | power_in | PLL supply voltage, 1.2 V. |+| 75 | EXTAL | input | Crystal oscillator input or external clock input (EXTCLK); EXTCLK operating voltage is 1.62 V to 3.6 V, EXTAL is 3.3 V. |+| 76 | XTAL | output | Crystal oscillator output; has no function in bypass mode and should then be grounded. |+| 77 | VSSPLL | power_in | PLL ground, connected to the same pin as VSSREG. |+| 78 | VDDEH6A | power_in | I/O supply input for the VDDEH6 segment, 3.3 V to 5.0 V; shorted with VDDEH6B in production packages. |+| 79 | VSS | power_in | Ground. |+| 80 | RESET | input | Active-low external reset input; internal reset asserts only if RESET is held for 10 clock cycles, weak pull-up after reset. |+| 81 | CAN_C_RX | bidirectional | CAN_C receive input, alternate GPIO[88]; slow pad, weak pull-up after reset. |+| 82 | SCI_A_RX | bidirectional | eSCI_A receive input, alternates eMIOS[15] and GPIO[90]; needs an external 10K pull-up for CAN serial boot. |+| 83 | SCI_A_TX | bidirectional | eSCI_A transmit output, alternates eMIOS[13] and GPIO[89]; slow pad, weak pull-up after reset. |+| 84 | CAN_C_TX | bidirectional | CAN_C transmit output, alternate GPIO[87]; medium pad, weak pull-up after reset. |+| 85 | RSTOUT | output | Active-low push/pull reset output driven low for all internal and external reset sources. |+| 86 | VDD | power_in | Internal logic supply input, 1.2 V. |+| 87 | DSPI_B_PCS[5] | bidirectional | DSPI_B peripheral chip select 5, alternates DSPI_C_PCS[0] and GPIO[110]; medium pad. |+| 88 | DSPI_B_PCS[4] | bidirectional | DSPI_B peripheral chip select 4, alternates DSPI_C_SCK and GPIO[109]; medium pad. |+| 89 | DSPI_B_SCK | bidirectional | DSPI_B clock (output in master, input in slave), alternates DSPI_C_PCS[1] and GPIO[102]; medium pad. |+| 90 | DSPI_B_PCS[2] | bidirectional | DSPI_B peripheral chip select 2, alternates DSPI_C_SOUT and GPIO[107]; medium pad. |+| 91 | VSS | power_in | Ground. |+| 92 | DSPI_B_PCS[1] | bidirectional | DSPI_B peripheral chip select 1, alternate GPIO[106]; medium pad. |+| 93 | VDDEH6B | power_in | I/O supply input for the VDDEH6 segment, 3.3 V to 5.0 V; shorted with VDDEH6A in production packages. |+| 94 | DSPI_B_PCS[0] | bidirectional | DSPI_B peripheral chip select 0 (slave select in slave mode), alternate GPIO[105]; medium pad. |+| 95 | DSPI_B_SIN | bidirectional | DSPI_B data input, alternates DSPI_C_PCS[2] and GPIO[103]; medium pad. |+| 96 | DSPI_B_SOUT | bidirectional | DSPI_B data output, alternates DSPI_C_PCS[5] and GPIO[104]; medium pad. |+| 97 | DSPI_B_PCS[3] | bidirectional | DSPI_B peripheral chip select 3, alternates DSPI_C_SIN and GPIO[108]; medium pad. |+| 98 | JCOMP | input | JTAG TAP controller enable input, weak pull-down after reset. |+| 99 | MCKO | output | Nexus message clock output (free-running clock for MDO/MSEO timing), alternate GPIO[219]. |+| 100 | TDO | output | JTAG serial test data output, alternates eMIOS[6] and GPIO[228]. |+| 101 | MSEO[1] | output | Nexus message start/end output, alternates eTPU_A[29] and GPIO[225]. |+| 102 | VDDEH7 | power_in | I/O supply input for the VDDEH7 segment, 3.3 V to 5.0 V; must be 5 V if JTAG or Nexus is used. |+| 103 | EVTI | input | Nexus event input read at RESET negation to enable the Nexus port, alternates eTPU_A[2] and GPIO[231]. |+| 104 | VSS | power_in | Ground. |+| 105 | TCK | input | JTAG test clock input, weak pull-down after reset. |+| 106 | EVTO | output | Nexus event output, alternates eTPU_A[4] and GPIO[227]. |+| 107 | TDI | input | JTAG serial test data input, alternates eMIOS[5] and GPIO[232]. |+| 108 | TMS | input | JTAG test mode select input, weak pull-up after reset. |+| 109 | MSEO[0] | output | Nexus message start/end output, alternates eTPU_A[27] and GPIO[224]. |+| 110 | MDO[0] | output | Nexus message data output 0, alternates eTPU_A[13] and GPIO[220]. |+| 111 | MDO[1] | output | Nexus message data output 1, alternates eTPU_A[19] and GPIO[221]. |+| 112 | MDO[2] | output | Nexus message data output 2, alternates eTPU_A[21] and GPIO[222]. |+| 113 | VDDEH7 | power_in | I/O supply input for the VDDEH7 segment, 3.3 V to 5.0 V; must be 5 V if JTAG or Nexus is used. |+| 114 | MDO[3] | output | Nexus message data output 3, alternates eTPU_A[25] and GPIO[223]. |+| 115 | VSS | power_in | Ground. |+| 116 | AN[15] | input | Single-ended analog input AN[15], alternates FCK (eQADC free running clock) and ETPU_A[29]; powered from VDDEH7. |+| 117 | AN[14] | input | Single-ended analog input AN[14], alternates MA[2], ETPU_A[27] and SDI (eQADC serial data in); powered from VDDEH7. |+| 118 | AN[13] | input | Single-ended analog input AN[13], alternates MA[1], ETPU_A[21] and SDO (eQADC serial data out); powered from VDDEH7. |+| 119 | AN[12] | input | Single-ended analog input AN[12], alternates MA[0], ETPU_A[19] and SDS (eQADC serial data strobe); powered from VDDEH7. |+| 120 | VDD | power_in | Internal logic supply input, 1.2 V. |+| 121 | AN[35] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 122 | AN[34] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 123 | AN[33] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 124 | AN[32] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 125 | AN[31] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 126 | AN[30] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 127 | AN[28] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 128 | AN[27] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 129 | AN[25] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 130 | AN[24] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 131 | AN[23] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 132 | AN[22] | input | Single-ended analog input to the eQADC, powered from VDDA. |+| 133 | VRL | input | eQADC voltage reference low input. |+| 134 | VRH | input | eQADC voltage reference high input. |+| 135 | REFBYPC | passive | eQADC reference bypass capacitor input. |+| 136 | AN[7] | input | Single-ended analog input AN[7], also negative terminal of differential input DAN3-. |+| 137 | AN[6] | input | Single-ended analog input AN[6], also positive terminal of differential input DAN3+. |+| 138 | AN[5] | input | Single-ended analog input AN[5], also negative terminal of differential input DAN2-. |+| 139 | AN[4] | input | Single-ended analog input AN[4], also positive terminal of differential input DAN2+. |+| 140 | AN[3] | input | Single-ended analog input AN[3], also negative terminal of differential input DAN1-. |+| 141 | AN[2] | input | Single-ended analog input AN[2], also positive terminal of differential input DAN1+. |+| 142 | AN[1] | input | Single-ended analog input AN[1], also negative terminal of differential input DAN0-. |+| 143 | AN[0] | input | Single-ended analog input AN[0], also positive terminal of differential input DAN0+. |+| 144 | AN[21] | input | Single-ended analog input to the eQADC, powered from VDDA. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-144(20x20) |+| Category | Embedded Processors & Controllers |+| Pins | 144 |++## CAD (KiCad official)++- Symbol: `SPC563M64L5COAY`+- Footprint: `Package_QFP:LQFP-144_20x20mm_P0.5mm`+- 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)+- 3D model files: `spc563m64l5coay-etched.step` / `spc563m64l5coay-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `spc563m64l5coay.step` / `spc563m64l5coay.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907760561344512) (128 pp, sha256 `495db481732ed0ef`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/spc563m64l5coay-datasheet.pdf)
page.jsonadded+1017@@ -0,0 +1,1017 @@+{+ "slug": "spc563m64l5coay",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "spc563m64l5coay",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "spc563m64l5coay.kicad_sym",+ "spc563m64l5coay.kicad_mod",+ "spc563m64l5coay.glb",+ "spc563m64l5coay.step",+ "spc563m64l5coay.lbr",+ "docs/hero.png",+ "docs/spc563m64l5coay-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "spc563m64l5coay-hero.glb",+ "spc563m64l5coay-hero.overlay.json"+ ],+ "component": {+ "mpn": "SPC563M64L5COAY",+ "manufacturer": "STMicroelectronics",+ "package": "LQFP-144(20x20)",+ "pin_count": 144,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907760561344512",+ "parts": {+ "symbol": "spc563m64l5coay.kicad_sym",+ "footprint": "spc563m64l5coay.kicad_mod",+ "model_3d": "spc563m64l5coay-hero.glb",+ "model_3d_plain": "spc563m64l5coay.glb",+ "model_3d_step": "spc563m64l5coay-etched.step",+ "model_3d_step_plain": "spc563m64l5coay.step",+ "lbr": "spc563m64l5coay.lbr"+ },+ "distributor_links": {+ "lcsc": "C503088",+ "digikey": "497-19141-ND",+ "mouser": "511-SPC563M64L5COAY"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T04:04:32Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-19141-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "511-SPC563M64L5COAY",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "AN[18]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "2",+ "name": "AN[17]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "3",+ "name": "AN[16]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "4",+ "name": "AN[11]",+ "type": "input",+ "description": "Single-ended analog input AN[11], also the ANZ external multiplexed analog input, powered from VDDA."+ },+ {+ "number": "5",+ "name": "AN[9]",+ "type": "input",+ "description": "Single-ended analog input AN[9], also the ANX external multiplexed analog input, powered from VDDA."+ },+ {+ "number": "6",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power input for the eQADC, nominal 5.0 V."+ },+ {+ "number": "7",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground input for the eQADC."+ },+ {+ "number": "8",+ "name": "AN[39]",+ "type": "input",+ "description": "Multiplexed single-ended analog input AN[39]/AN[10]/ANY, powered from VDDA."+ },+ {+ "number": "9",+ "name": "AN[38]",+ "type": "input",+ "description": "Multiplexed single-ended analog input AN[38]/AN[8]/ANW, powered from VDDA."+ },+ {+ "number": "10",+ "name": "VDDREG",+ "type": "power_in",+ "description": "Voltage regulator supply input, nominal 5.0 V."+ },+ {+ "number": "11",+ "name": "VRCCTL",+ "type": "output",+ "description": "Voltage regulator control output that drives the external pass transistor for the 1.2 V supply."+ },+ {+ "number": "12",+ "name": "VSTBY",+ "type": "power_in",+ "description": "Power supply for the standby RAM."+ },+ {+ "number": "13",+ "name": "VRC33",+ "type": "passive",+ "description": "3.3 V voltage regulator bypass capacitor connection."+ },+ {+ "number": "14",+ "name": "eTPU_A[31]",+ "type": "bidirectional",+ "description": "eTPU_A channel 31, alternates DSPI_C_PCS[4], eTPU_A[13] and GPIO[145]; medium pad powered from VDDEH1."+ },+ {+ "number": "15",+ "name": "eTPU_A[30]",+ "type": "bidirectional",+ "description": "eTPU_A channel 30, alternates DSPI_C_PCS[3], eTPU_A[11] and GPIO[144]; medium pad powered from VDDEH1."+ },+ {+ "number": "16",+ "name": "eTPU_A[29]",+ "type": "bidirectional",+ "description": "eTPU_A channel 29 (input and output), alternates DSPI_C_PCS[2] and GPIO[143]; medium pad."+ },+ {+ "number": "17",+ "name": "eTPU_A[28]",+ "type": "bidirectional",+ "description": "eTPU_A channel 28 (input and output), alternates DSPI_C_PCS[1] and GPIO[142]; medium pad."+ },+ {+ "number": "18",+ "name": "eTPU_A[27]",+ "type": "bidirectional",+ "description": "eTPU_A channel 27 (input and output), alternates IRQ[15], DSPI_C_SOUT_LVDS+, DSPI_B_SOUT and GPIO[141]; slow pad."+ },+ {+ "number": "19",+ "name": "eTPU_A[26]",+ "type": "bidirectional",+ "description": "eTPU_A channel 26 (input and output), alternates IRQ[14], DSPI_C_SOUT_LVDS- and GPIO[140]; slow pad."+ },+ {+ "number": "20",+ "name": "eTPU_A[25]",+ "type": "bidirectional",+ "description": "eTPU_A channel 25 (input and output), alternates IRQ[13], DSPI_C_SCK_LVDS+ and GPIO[139]; medium pad."+ },+ {+ "number": "21",+ "name": "eTPU_A[24]",+ "type": "bidirectional",+ "description": "eTPU_A channel 24 (input and output), alternates IRQ[12], DSPI_C_SCK_LVDS- and GPIO[138]; slow pad."+ },+ {+ "number": "22",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "23",+ "name": "eTPU_A[23]",+ "type": "bidirectional",+ "description": "eTPU_A channel 23, alternates IRQ[11], eTPU_A[21] and GPIO[137]; slow pad."+ },+ {+ "number": "24",+ "name": "VDDEH1A",+ "type": "power_in",+ "description": "I/O supply input for the VDDEH1 segment, 3.3 V to 5.0 V; shorted with VDDEH1B in production packages."+ },+ {+ "number": "25",+ "name": "eTPU_A[22]",+ "type": "bidirectional",+ "description": "eTPU_A channel 22, alternates IRQ[10], eTPU_A[17] and GPIO[136]; slow pad."+ },+ {+ "number": "26",+ "name": "VDD",+ "type": "power_in",+ "description": "Internal logic supply input, 1.2 V."+ },+ {+ "number": "27",+ "name": "eTPU_A[21]",+ "type": "bidirectional",+ "description": "eTPU_A channel 21, alternates IRQ[9] and GPIO[135]; slow pad."+ },+ {+ "number": "28",+ "name": "eTPU_A[20]",+ "type": "bidirectional",+ "description": "eTPU_A channel 20, alternates IRQ[8] and GPIO[134]; slow pad."+ },+ {+ "number": "29",+ "name": "eTPU_A[19]",+ "type": "bidirectional",+ "description": "eTPU_A channel 19, alternate GPIO[133]; slow pad."+ },+ {+ "number": "30",+ "name": "eTPU_A[18]",+ "type": "bidirectional",+ "description": "eTPU_A channel 18, alternate GPIO[132]; slow pad."+ },+ {+ "number": "31",+ "name": "eTPU_A[17]",+ "type": "bidirectional",+ "description": "eTPU_A channel 17, alternate GPIO[131]; slow pad."+ },+ {+ "number": "32",+ "name": "eTPU_A[16]",+ "type": "bidirectional",+ "description": "eTPU_A channel 16, alternate GPIO[130]; slow pad."+ },+ {+ "number": "33",+ "name": "eTPU_A[15]",+ "type": "bidirectional",+ "description": "eTPU_A channel 15, alternates DSPI_B_PCS[5] and GPIO[129]; medium pad."+ },+ {+ "number": "34",+ "name": "VDDEH1B",+ "type": "power_in",+ "description": "I/O supply input for the VDDEH1 segment, 3.3 V to 5.0 V; shorted with VDDEH1A in production packages."+ },+ {+ "number": "35",+ "name": "eTPU_A[14]",+ "type": "bidirectional",+ "description": "eTPU_A channel 14, alternates DSPI_B_PCS[4], eTPU_A[9] and GPIO[128]; medium pad."+ },+ {+ "number": "36",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "37",+ "name": "eTPU_A[13]",+ "type": "bidirectional",+ "description": "eTPU_A channel 13, alternates DSPI_B_PCS[3] and GPIO[127]; medium pad."+ },+ {+ "number": "38",+ "name": "eTPU_A[12]",+ "type": "bidirectional",+ "description": "eTPU_A channel 12, alternates DSPI_B_PCS[1] and GPIO[126]; medium pad."+ },+ {+ "number": "39",+ "name": "eTPU_A[11]",+ "type": "bidirectional",+ "description": "eTPU_A channel 11, alternates eTPU_A[23] and GPIO[125]; slow pad."+ },+ {+ "number": "40",+ "name": "eTPU_A[10]",+ "type": "bidirectional",+ "description": "eTPU_A channel 10, alternates eTPU_A[22] and GPIO[124]; slow pad."+ },+ {+ "number": "41",+ "name": "eTPU_A[9]",+ "type": "bidirectional",+ "description": "eTPU_A channel 9, alternates eTPU_A[21] and GPIO[123]; slow pad."+ },+ {+ "number": "42",+ "name": "eTPU_A[8]",+ "type": "bidirectional",+ "description": "eTPU_A channel 8, alternates eTPU_A[20], DSPI_B_SOUT_LVDS+ and GPIO[122]; slow pad."+ },+ {+ "number": "43",+ "name": "eTPU_A[7]",+ "type": "bidirectional",+ "description": "eTPU_A channel 7, alternates eTPU_A[19], DSPI_B_SOUT_LVDS-, eTPU_A[6] and GPIO[121]; slow pad."+ },+ {+ "number": "44",+ "name": "eTPU_A[6]",+ "type": "bidirectional",+ "description": "eTPU_A channel 6, alternates eTPU_A[18], DSPI_B_SCK_LVDS+ and GPIO[120]; medium pad."+ },+ {+ "number": "45",+ "name": "eTPU_A[5]",+ "type": "bidirectional",+ "description": "eTPU_A channel 5, alternates eTPU_A[17], DSPI_B_SCK_LVDS- and GPIO[119]; slow pad."+ },+ {+ "number": "46",+ "name": "VDDEH1B",+ "type": "power_in",+ "description": "I/O supply input for the VDDEH1 segment, 3.3 V to 5.0 V; shorted with VDDEH1A in production packages."+ },+ {+ "number": "47",+ "name": "eTPU_A[4]",+ "type": "bidirectional",+ "description": "eTPU_A channel 4, alternates eTPU_A[16] and GPIO[118]; slow pad."+ },+ {+ "number": "48",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "49",+ "name": "eTPU_A[3]",+ "type": "bidirectional",+ "description": "eTPU_A channel 3, alternates eTPU_A[15] and GPIO[117]; slow pad."+ },+ {+ "number": "50",+ "name": "eTPU_A[2]",+ "type": "bidirectional",+ "description": "eTPU_A channel 2, alternates eTPU_A[14] and GPIO[116]; slow pad."+ },+ {+ "number": "51",+ "name": "eTPU_A[1]",+ "type": "bidirectional",+ "description": "eTPU_A channel 1, alternates eTPU_A[13] and GPIO[115]; slow pad."+ },+ {+ "number": "52",+ "name": "eTPU_A[0]",+ "type": "bidirectional",+ "description": "eTPU_A channel 0, alternates eTPU_A[12], eTPU_A[19] and GPIO[114]; slow pad."+ },+ {+ "number": "53",+ "name": "VDD",+ "type": "power_in",+ "description": "Internal logic supply input, 1.2 V."+ },+ {+ "number": "54",+ "name": "eMIOS[0]",+ "type": "bidirectional",+ "description": "eMIOS channel 0, alternates eTPU_A[0], eTPU_A[25] (output only) and GPIO[179]; slow pad."+ },+ {+ "number": "55",+ "name": "eMIOS[2]",+ "type": "bidirectional",+ "description": "eMIOS channel 2, alternates eTPU_A[2] and GPIO[181]; slow pad."+ },+ {+ "number": "56",+ "name": "eMIOS[4]",+ "type": "bidirectional",+ "description": "eMIOS channel 4, alternates eTPU_A[4] and GPIO[183]; slow pad on VDDEH6a."+ },+ {+ "number": "57",+ "name": "eMIOS[8]",+ "type": "bidirectional",+ "description": "eMIOS channel 8, alternates eTPU_A[8] (output only), SCI_B_TX and GPIO[187]; slow pad."+ },+ {+ "number": "58",+ "name": "eMIOS[9]",+ "type": "bidirectional",+ "description": "eMIOS channel 9, alternates eTPU_A[9] (output only), SCI_B_RX and GPIO[188]; slow pad."+ },+ {+ "number": "59",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "60",+ "name": "eMIOS[10]",+ "type": "bidirectional",+ "description": "eMIOS channel 10, alternate GPIO[189]; slow pad."+ },+ {+ "number": "61",+ "name": "VDDEH6A",+ "type": "power_in",+ "description": "I/O supply input for the VDDEH6 segment, 3.3 V to 5.0 V; shorted with VDDEH6B in production packages."+ },+ {+ "number": "62",+ "name": "eMIOS[11]",+ "type": "bidirectional",+ "description": "eMIOS channel 11, alternate GPIO[190]; slow pad."+ },+ {+ "number": "63",+ "name": "eMIOS[12]",+ "type": "bidirectional",+ "description": "eMIOS channel 12, alternates DSPI_C_SOUT, eTPU_A[27] and GPIO[191]; medium pad."+ },+ {+ "number": "64",+ "name": "eMIOS[14]",+ "type": "bidirectional",+ "description": "eMIOS channel 14, alternates IRQ[0], eTPU_A[29] and GPIO[193]; slow pad."+ },+ {+ "number": "65",+ "name": "eMIOS[23]",+ "type": "bidirectional",+ "description": "eMIOS channel 23, alternate GPIO[202]; slow pad."+ },+ {+ "number": "66",+ "name": "CAN_A_TX",+ "type": "bidirectional",+ "description": "CAN_A transmit output, alternates SCI_A_TX and GPIO[83]; slow pad, weak pull-up after reset."+ },+ {+ "number": "67",+ "name": "CAN_A_RX",+ "type": "bidirectional",+ "description": "CAN_A receive input, alternates SCI_A_RX and GPIO[84]; slow pad, weak pull-up after reset."+ },+ {+ "number": "68",+ "name": "PLLREF",+ "type": "input",+ "description": "FMPLL mode selection at reset (PLLREF=0 selects external reference mode), alternates IRQ[4], ETRIG[2] and GPIO[208]."+ },+ {+ "number": "69",+ "name": "SCI_B_RX",+ "type": "bidirectional",+ "description": "eSCI_B receive input, alternate GPIO[92]; slow pad, weak pull-up after reset."+ },+ {+ "number": "70",+ "name": "BOOTCFG1",+ "type": "input",+ "description": "Boot configuration input sampled during RSTOUT assertion (0 = internal flash boot, 1 = FlexCAN/eSCI boot), alternates IRQ[3], ETRIG[3] and GPIO[212]."+ },+ {+ "number": "71",+ "name": "WKPCFG",+ "type": "input",+ "description": "Weak pull configuration input latched at reset to select pull-up or pull-down on eTPU and eMIOS pins, alternates NMI, DSPI_B_SOUT and GPIO[213]."+ },+ {+ "number": "72",+ "name": "SCI_B_TX",+ "type": "bidirectional",+ "description": "eSCI_B transmit output, alternate GPIO[91]; slow pad, weak pull-up after reset."+ },+ {+ "number": "73",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "74",+ "name": "VDDPLL",+ "type": "power_in",+ "description": "PLL supply voltage, 1.2 V."+ },+ {+ "number": "75",+ "name": "EXTAL",+ "type": "input",+ "description": "Crystal oscillator input or external clock input (EXTCLK); EXTCLK operating voltage is 1.62 V to 3.6 V, EXTAL is 3.3 V."+ },+ {+ "number": "76",+ "name": "XTAL",+ "type": "output",+ "description": "Crystal oscillator output; has no function in bypass mode and should then be grounded."+ },+ {+ "number": "77",+ "name": "VSSPLL",+ "type": "power_in",+ "description": "PLL ground, connected to the same pin as VSSREG."+ },+ {+ "number": "78",+ "name": "VDDEH6A",+ "type": "power_in",+ "description": "I/O supply input for the VDDEH6 segment, 3.3 V to 5.0 V; shorted with VDDEH6B in production packages."+ },+ {+ "number": "79",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "80",+ "name": "RESET",+ "type": "input",+ "description": "Active-low external reset input; internal reset asserts only if RESET is held for 10 clock cycles, weak pull-up after reset."+ },+ {+ "number": "81",+ "name": "CAN_C_RX",+ "type": "bidirectional",+ "description": "CAN_C receive input, alternate GPIO[88]; slow pad, weak pull-up after reset."+ },+ {+ "number": "82",+ "name": "SCI_A_RX",+ "type": "bidirectional",+ "description": "eSCI_A receive input, alternates eMIOS[15] and GPIO[90]; needs an external 10K pull-up for CAN serial boot."+ },+ {+ "number": "83",+ "name": "SCI_A_TX",+ "type": "bidirectional",+ "description": "eSCI_A transmit output, alternates eMIOS[13] and GPIO[89]; slow pad, weak pull-up after reset."+ },+ {+ "number": "84",+ "name": "CAN_C_TX",+ "type": "bidirectional",+ "description": "CAN_C transmit output, alternate GPIO[87]; medium pad, weak pull-up after reset."+ },+ {+ "number": "85",+ "name": "RSTOUT",+ "type": "output",+ "description": "Active-low push/pull reset output driven low for all internal and external reset sources."+ },+ {+ "number": "86",+ "name": "VDD",+ "type": "power_in",+ "description": "Internal logic supply input, 1.2 V."+ },+ {+ "number": "87",+ "name": "DSPI_B_PCS[5]",+ "type": "bidirectional",+ "description": "DSPI_B peripheral chip select 5, alternates DSPI_C_PCS[0] and GPIO[110]; medium pad."+ },+ {+ "number": "88",+ "name": "DSPI_B_PCS[4]",+ "type": "bidirectional",+ "description": "DSPI_B peripheral chip select 4, alternates DSPI_C_SCK and GPIO[109]; medium pad."+ },+ {+ "number": "89",+ "name": "DSPI_B_SCK",+ "type": "bidirectional",+ "description": "DSPI_B clock (output in master, input in slave), alternates DSPI_C_PCS[1] and GPIO[102]; medium pad."+ },+ {+ "number": "90",+ "name": "DSPI_B_PCS[2]",+ "type": "bidirectional",+ "description": "DSPI_B peripheral chip select 2, alternates DSPI_C_SOUT and GPIO[107]; medium pad."+ },+ {+ "number": "91",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "92",+ "name": "DSPI_B_PCS[1]",+ "type": "bidirectional",+ "description": "DSPI_B peripheral chip select 1, alternate GPIO[106]; medium pad."+ },+ {+ "number": "93",+ "name": "VDDEH6B",+ "type": "power_in",+ "description": "I/O supply input for the VDDEH6 segment, 3.3 V to 5.0 V; shorted with VDDEH6A in production packages."+ },+ {+ "number": "94",+ "name": "DSPI_B_PCS[0]",+ "type": "bidirectional",+ "description": "DSPI_B peripheral chip select 0 (slave select in slave mode), alternate GPIO[105]; medium pad."+ },+ {+ "number": "95",+ "name": "DSPI_B_SIN",+ "type": "bidirectional",+ "description": "DSPI_B data input, alternates DSPI_C_PCS[2] and GPIO[103]; medium pad."+ },+ {+ "number": "96",+ "name": "DSPI_B_SOUT",+ "type": "bidirectional",+ "description": "DSPI_B data output, alternates DSPI_C_PCS[5] and GPIO[104]; medium pad."+ },+ {+ "number": "97",+ "name": "DSPI_B_PCS[3]",+ "type": "bidirectional",+ "description": "DSPI_B peripheral chip select 3, alternates DSPI_C_SIN and GPIO[108]; medium pad."+ },+ {+ "number": "98",+ "name": "JCOMP",+ "type": "input",+ "description": "JTAG TAP controller enable input, weak pull-down after reset."+ },+ {+ "number": "99",+ "name": "MCKO",+ "type": "output",+ "description": "Nexus message clock output (free-running clock for MDO/MSEO timing), alternate GPIO[219]."+ },+ {+ "number": "100",+ "name": "TDO",+ "type": "output",+ "description": "JTAG serial test data output, alternates eMIOS[6] and GPIO[228]."+ },+ {+ "number": "101",+ "name": "MSEO[1]",+ "type": "output",+ "description": "Nexus message start/end output, alternates eTPU_A[29] and GPIO[225]."+ },+ {+ "number": "102",+ "name": "VDDEH7",+ "type": "power_in",+ "description": "I/O supply input for the VDDEH7 segment, 3.3 V to 5.0 V; must be 5 V if JTAG or Nexus is used."+ },+ {+ "number": "103",+ "name": "EVTI",+ "type": "input",+ "description": "Nexus event input read at RESET negation to enable the Nexus port, alternates eTPU_A[2] and GPIO[231]."+ },+ {+ "number": "104",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "105",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock input, weak pull-down after reset."+ },+ {+ "number": "106",+ "name": "EVTO",+ "type": "output",+ "description": "Nexus event output, alternates eTPU_A[4] and GPIO[227]."+ },+ {+ "number": "107",+ "name": "TDI",+ "type": "input",+ "description": "JTAG serial test data input, alternates eMIOS[5] and GPIO[232]."+ },+ {+ "number": "108",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test mode select input, weak pull-up after reset."+ },+ {+ "number": "109",+ "name": "MSEO[0]",+ "type": "output",+ "description": "Nexus message start/end output, alternates eTPU_A[27] and GPIO[224]."+ },+ {+ "number": "110",+ "name": "MDO[0]",+ "type": "output",+ "description": "Nexus message data output 0, alternates eTPU_A[13] and GPIO[220]."+ },+ {+ "number": "111",+ "name": "MDO[1]",+ "type": "output",+ "description": "Nexus message data output 1, alternates eTPU_A[19] and GPIO[221]."+ },+ {+ "number": "112",+ "name": "MDO[2]",+ "type": "output",+ "description": "Nexus message data output 2, alternates eTPU_A[21] and GPIO[222]."+ },+ {+ "number": "113",+ "name": "VDDEH7",+ "type": "power_in",+ "description": "I/O supply input for the VDDEH7 segment, 3.3 V to 5.0 V; must be 5 V if JTAG or Nexus is used."+ },+ {+ "number": "114",+ "name": "MDO[3]",+ "type": "output",+ "description": "Nexus message data output 3, alternates eTPU_A[25] and GPIO[223]."+ },+ {+ "number": "115",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "116",+ "name": "AN[15]",+ "type": "input",+ "description": "Single-ended analog input AN[15], alternates FCK (eQADC free running clock) and ETPU_A[29]; powered from VDDEH7."+ },+ {+ "number": "117",+ "name": "AN[14]",+ "type": "input",+ "description": "Single-ended analog input AN[14], alternates MA[2], ETPU_A[27] and SDI (eQADC serial data in); powered from VDDEH7."+ },+ {+ "number": "118",+ "name": "AN[13]",+ "type": "input",+ "description": "Single-ended analog input AN[13], alternates MA[1], ETPU_A[21] and SDO (eQADC serial data out); powered from VDDEH7."+ },+ {+ "number": "119",+ "name": "AN[12]",+ "type": "input",+ "description": "Single-ended analog input AN[12], alternates MA[0], ETPU_A[19] and SDS (eQADC serial data strobe); powered from VDDEH7."+ },+ {+ "number": "120",+ "name": "VDD",+ "type": "power_in",+ "description": "Internal logic supply input, 1.2 V."+ },+ {+ "number": "121",+ "name": "AN[35]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "122",+ "name": "AN[34]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "123",+ "name": "AN[33]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "124",+ "name": "AN[32]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "125",+ "name": "AN[31]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "126",+ "name": "AN[30]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "127",+ "name": "AN[28]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "128",+ "name": "AN[27]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "129",+ "name": "AN[25]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "130",+ "name": "AN[24]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "131",+ "name": "AN[23]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "132",+ "name": "AN[22]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ },+ {+ "number": "133",+ "name": "VRL",+ "type": "input",+ "description": "eQADC voltage reference low input."+ },+ {+ "number": "134",+ "name": "VRH",+ "type": "input",+ "description": "eQADC voltage reference high input."+ },+ {+ "number": "135",+ "name": "REFBYPC",+ "type": "passive",+ "description": "eQADC reference bypass capacitor input."+ },+ {+ "number": "136",+ "name": "AN[7]",+ "type": "input",+ "description": "Single-ended analog input AN[7], also negative terminal of differential input DAN3-."+ },+ {+ "number": "137",+ "name": "AN[6]",+ "type": "input",+ "description": "Single-ended analog input AN[6], also positive terminal of differential input DAN3+."+ },+ {+ "number": "138",+ "name": "AN[5]",+ "type": "input",+ "description": "Single-ended analog input AN[5], also negative terminal of differential input DAN2-."+ },+ {+ "number": "139",+ "name": "AN[4]",+ "type": "input",+ "description": "Single-ended analog input AN[4], also positive terminal of differential input DAN2+."+ },+ {+ "number": "140",+ "name": "AN[3]",+ "type": "input",+ "description": "Single-ended analog input AN[3], also negative terminal of differential input DAN1-."+ },+ {+ "number": "141",+ "name": "AN[2]",+ "type": "input",+ "description": "Single-ended analog input AN[2], also positive terminal of differential input DAN1+."+ },+ {+ "number": "142",+ "name": "AN[1]",+ "type": "input",+ "description": "Single-ended analog input AN[1], also negative terminal of differential input DAN0-."+ },+ {+ "number": "143",+ "name": "AN[0]",+ "type": "input",+ "description": "Single-ended analog input AN[0], also positive terminal of differential input DAN0+."+ },+ {+ "number": "144",+ "name": "AN[21]",+ "type": "input",+ "description": "Single-ended analog input to the eQADC, powered from VDDA."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Figure 2 (144-pin LQFP top view) is scrambled in the text extraction, so pin numbers were taken from; Some signal names differ between Figure 2 and Table 4 (e.g., pin 20/21/27/28 DSPI_C_SCK_LVDS vs SCK_; Pin 61 is labelled VDDEH6A in Figure 2 and VDDEH6b in Table 4; the datasheet states VDDEH6A and VDDE",+ "2/144 pins cited to the wrong page (name found elsewhere): ['80:RESET@p66', '85:RSTOUT@p66']"+ ],+ "pages_sent": 52,+ "cost_usd": 0.3913,+ "at": "2026-10-08T04:03:48"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907760561344512",+ "pages": 128,+ "sha256": "495db481732ed0ef",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 144,+ "described": 144,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "spc563m64l5coay.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 22,+ 22,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b4d698da8bb7697b754adb5655c932342462d9b9341cdaa081b3604dbdf7559b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "spc563m64l5coay-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 22,+ 22,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "0ea122eaaa4ee916efb47a5028ba206468bcbb6353383a318679aeefcf249dce",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}