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SPC563M64L5COAY

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersspc563m64l5coayfactory-2.0.0extractor-text
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Symbol & Footprint

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Datasheet

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Contents

README

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SPC563M64L5COAY

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

SPC563M64L5COAY from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AN[18] input Single-ended analog input to the eQADC, powered from VDDA.
2 AN[17] input Single-ended analog input to the eQADC, powered from VDDA.
3 AN[16] input Single-ended analog input to the eQADC, powered from VDDA.
4 AN[11] input Single-ended analog input AN[11], also the ANZ external multiplexed analog input, powered from VDDA.
5 AN[9] input Single-ended analog input AN[9], also the ANX external multiplexed analog input, powered from VDDA.
6 VDDA power_in Analog power input for the eQADC, nominal 5.0 V.
7 VSSA power_in Analog ground input for the eQADC.
8 AN[39] input Multiplexed single-ended analog input AN[39]/AN[10]/ANY, powered from VDDA.
9 AN[38] input Multiplexed single-ended analog input AN[38]/AN[8]/ANW, powered from VDDA.
10 VDDREG power_in Voltage regulator supply input, nominal 5.0 V.
11 VRCCTL output Voltage regulator control output that drives the external pass transistor for the 1.2 V supply.
12 VSTBY power_in Power supply for the standby RAM.
13 VRC33 passive 3.3 V voltage regulator bypass capacitor connection.
14 eTPU_A[31] bidirectional eTPU_A channel 31, alternates DSPI_C_PCS[4], eTPU_A[13] and GPIO[145]; medium pad powered from VDDEH1.
15 eTPU_A[30] bidirectional eTPU_A channel 30, alternates DSPI_C_PCS[3], eTPU_A[11] and GPIO[144]; medium pad powered from VDDEH1.
16 eTPU_A[29] bidirectional eTPU_A channel 29 (input and output), alternates DSPI_C_PCS[2] and GPIO[143]; medium pad.
17 eTPU_A[28] bidirectional eTPU_A channel 28 (input and output), alternates DSPI_C_PCS[1] and GPIO[142]; medium pad.
18 eTPU_A[27] bidirectional eTPU_A channel 27 (input and output), alternates IRQ[15], DSPI_C_SOUT_LVDS+, DSPI_B_SOUT and GPIO[141]; slow pad.
19 eTPU_A[26] bidirectional eTPU_A channel 26 (input and output), alternates IRQ[14], DSPI_C_SOUT_LVDS- and GPIO[140]; slow pad.
20 eTPU_A[25] bidirectional eTPU_A channel 25 (input and output), alternates IRQ[13], DSPI_C_SCK_LVDS+ and GPIO[139]; medium pad.
21 eTPU_A[24] bidirectional eTPU_A channel 24 (input and output), alternates IRQ[12], DSPI_C_SCK_LVDS- and GPIO[138]; slow pad.
22 VSS power_in Ground.
23 eTPU_A[23] bidirectional eTPU_A channel 23, alternates IRQ[11], eTPU_A[21] and GPIO[137]; slow pad.
24 VDDEH1A power_in I/O supply input for the VDDEH1 segment, 3.3 V to 5.0 V; shorted with VDDEH1B in production packages.
25 eTPU_A[22] bidirectional eTPU_A channel 22, alternates IRQ[10], eTPU_A[17] and GPIO[136]; slow pad.
26 VDD power_in Internal logic supply input, 1.2 V.
27 eTPU_A[21] bidirectional eTPU_A channel 21, alternates IRQ[9] and GPIO[135]; slow pad.
28 eTPU_A[20] bidirectional eTPU_A channel 20, alternates IRQ[8] and GPIO[134]; slow pad.
29 eTPU_A[19] bidirectional eTPU_A channel 19, alternate GPIO[133]; slow pad.
30 eTPU_A[18] bidirectional eTPU_A channel 18, alternate GPIO[132]; slow pad.
31 eTPU_A[17] bidirectional eTPU_A channel 17, alternate GPIO[131]; slow pad.
32 eTPU_A[16] bidirectional eTPU_A channel 16, alternate GPIO[130]; slow pad.
33 eTPU_A[15] bidirectional eTPU_A channel 15, alternates DSPI_B_PCS[5] and GPIO[129]; medium pad.
34 VDDEH1B power_in I/O supply input for the VDDEH1 segment, 3.3 V to 5.0 V; shorted with VDDEH1A in production packages.
35 eTPU_A[14] bidirectional eTPU_A channel 14, alternates DSPI_B_PCS[4], eTPU_A[9] and GPIO[128]; medium pad.
36 VSS power_in Ground.
37 eTPU_A[13] bidirectional eTPU_A channel 13, alternates DSPI_B_PCS[3] and GPIO[127]; medium pad.
38 eTPU_A[12] bidirectional eTPU_A channel 12, alternates DSPI_B_PCS[1] and GPIO[126]; medium pad.
39 eTPU_A[11] bidirectional eTPU_A channel 11, alternates eTPU_A[23] and GPIO[125]; slow pad.
40 eTPU_A[10] bidirectional eTPU_A channel 10, alternates eTPU_A[22] and GPIO[124]; slow pad.
41 eTPU_A[9] bidirectional eTPU_A channel 9, alternates eTPU_A[21] and GPIO[123]; slow pad.
42 eTPU_A[8] bidirectional eTPU_A channel 8, alternates eTPU_A[20], DSPI_B_SOUT_LVDS+ and GPIO[122]; slow pad.
43 eTPU_A[7] bidirectional eTPU_A channel 7, alternates eTPU_A[19], DSPI_B_SOUT_LVDS-, eTPU_A[6] and GPIO[121]; slow pad.
44 eTPU_A[6] bidirectional eTPU_A channel 6, alternates eTPU_A[18], DSPI_B_SCK_LVDS+ and GPIO[120]; medium pad.
45 eTPU_A[5] bidirectional eTPU_A channel 5, alternates eTPU_A[17], DSPI_B_SCK_LVDS- and GPIO[119]; slow pad.
46 VDDEH1B power_in I/O supply input for the VDDEH1 segment, 3.3 V to 5.0 V; shorted with VDDEH1A in production packages.
47 eTPU_A[4] bidirectional eTPU_A channel 4, alternates eTPU_A[16] and GPIO[118]; slow pad.
48 VSS power_in Ground.
49 eTPU_A[3] bidirectional eTPU_A channel 3, alternates eTPU_A[15] and GPIO[117]; slow pad.
50 eTPU_A[2] bidirectional eTPU_A channel 2, alternates eTPU_A[14] and GPIO[116]; slow pad.
51 eTPU_A[1] bidirectional eTPU_A channel 1, alternates eTPU_A[13] and GPIO[115]; slow pad.
52 eTPU_A[0] bidirectional eTPU_A channel 0, alternates eTPU_A[12], eTPU_A[19] and GPIO[114]; slow pad.
53 VDD power_in Internal logic supply input, 1.2 V.
54 eMIOS[0] bidirectional eMIOS channel 0, alternates eTPU_A[0], eTPU_A[25] (output only) and GPIO[179]; slow pad.
55 eMIOS[2] bidirectional eMIOS channel 2, alternates eTPU_A[2] and GPIO[181]; slow pad.
56 eMIOS[4] bidirectional eMIOS channel 4, alternates eTPU_A[4] and GPIO[183]; slow pad on VDDEH6a.
57 eMIOS[8] bidirectional eMIOS channel 8, alternates eTPU_A[8] (output only), SCI_B_TX and GPIO[187]; slow pad.
58 eMIOS[9] bidirectional eMIOS channel 9, alternates eTPU_A[9] (output only), SCI_B_RX and GPIO[188]; slow pad.
59 VSS power_in Ground.
60 eMIOS[10] bidirectional eMIOS channel 10, alternate GPIO[189]; slow pad.
61 VDDEH6A power_in I/O supply input for the VDDEH6 segment, 3.3 V to 5.0 V; shorted with VDDEH6B in production packages.
62 eMIOS[11] bidirectional eMIOS channel 11, alternate GPIO[190]; slow pad.
63 eMIOS[12] bidirectional eMIOS channel 12, alternates DSPI_C_SOUT, eTPU_A[27] and GPIO[191]; medium pad.
64 eMIOS[14] bidirectional eMIOS channel 14, alternates IRQ[0], eTPU_A[29] and GPIO[193]; slow pad.
65 eMIOS[23] bidirectional eMIOS channel 23, alternate GPIO[202]; slow pad.
66 CAN_A_TX bidirectional CAN_A transmit output, alternates SCI_A_TX and GPIO[83]; slow pad, weak pull-up after reset.
67 CAN_A_RX bidirectional CAN_A receive input, alternates SCI_A_RX and GPIO[84]; slow pad, weak pull-up after reset.
68 PLLREF input FMPLL mode selection at reset (PLLREF=0 selects external reference mode), alternates IRQ[4], ETRIG[2] and GPIO[208].
69 SCI_B_RX bidirectional eSCI_B receive input, alternate GPIO[92]; slow pad, weak pull-up after reset.
70 BOOTCFG1 input Boot configuration input sampled during RSTOUT assertion (0 = internal flash boot, 1 = FlexCAN/eSCI boot), alternates IRQ[3], ETRIG[3] and GPIO[212].
71 WKPCFG input Weak pull configuration input latched at reset to select pull-up or pull-down on eTPU and eMIOS pins, alternates NMI, DSPI_B_SOUT and GPIO[213].
72 SCI_B_TX bidirectional eSCI_B transmit output, alternate GPIO[91]; slow pad, weak pull-up after reset.
73 VSS power_in Ground.
74 VDDPLL power_in PLL supply voltage, 1.2 V.
75 EXTAL input Crystal oscillator input or external clock input (EXTCLK); EXTCLK operating voltage is 1.62 V to 3.6 V, EXTAL is 3.3 V.
76 XTAL output Crystal oscillator output; has no function in bypass mode and should then be grounded.
77 VSSPLL power_in PLL ground, connected to the same pin as VSSREG.
78 VDDEH6A power_in I/O supply input for the VDDEH6 segment, 3.3 V to 5.0 V; shorted with VDDEH6B in production packages.
79 VSS power_in Ground.
80 RESET input Active-low external reset input; internal reset asserts only if RESET is held for 10 clock cycles, weak pull-up after reset.
81 CAN_C_RX bidirectional CAN_C receive input, alternate GPIO[88]; slow pad, weak pull-up after reset.
82 SCI_A_RX bidirectional eSCI_A receive input, alternates eMIOS[15] and GPIO[90]; needs an external 10K pull-up for CAN serial boot.
83 SCI_A_TX bidirectional eSCI_A transmit output, alternates eMIOS[13] and GPIO[89]; slow pad, weak pull-up after reset.
84 CAN_C_TX bidirectional CAN_C transmit output, alternate GPIO[87]; medium pad, weak pull-up after reset.
85 RSTOUT output Active-low push/pull reset output driven low for all internal and external reset sources.
86 VDD power_in Internal logic supply input, 1.2 V.
87 DSPI_B_PCS[5] bidirectional DSPI_B peripheral chip select 5, alternates DSPI_C_PCS[0] and GPIO[110]; medium pad.
88 DSPI_B_PCS[4] bidirectional DSPI_B peripheral chip select 4, alternates DSPI_C_SCK and GPIO[109]; medium pad.
89 DSPI_B_SCK bidirectional DSPI_B clock (output in master, input in slave), alternates DSPI_C_PCS[1] and GPIO[102]; medium pad.
90 DSPI_B_PCS[2] bidirectional DSPI_B peripheral chip select 2, alternates DSPI_C_SOUT and GPIO[107]; medium pad.
91 VSS power_in Ground.
92 DSPI_B_PCS[1] bidirectional DSPI_B peripheral chip select 1, alternate GPIO[106]; medium pad.
93 VDDEH6B power_in I/O supply input for the VDDEH6 segment, 3.3 V to 5.0 V; shorted with VDDEH6A in production packages.
94 DSPI_B_PCS[0] bidirectional DSPI_B peripheral chip select 0 (slave select in slave mode), alternate GPIO[105]; medium pad.
95 DSPI_B_SIN bidirectional DSPI_B data input, alternates DSPI_C_PCS[2] and GPIO[103]; medium pad.
96 DSPI_B_SOUT bidirectional DSPI_B data output, alternates DSPI_C_PCS[5] and GPIO[104]; medium pad.
97 DSPI_B_PCS[3] bidirectional DSPI_B peripheral chip select 3, alternates DSPI_C_SIN and GPIO[108]; medium pad.
98 JCOMP input JTAG TAP controller enable input, weak pull-down after reset.
99 MCKO output Nexus message clock output (free-running clock for MDO/MSEO timing), alternate GPIO[219].
100 TDO output JTAG serial test data output, alternates eMIOS[6] and GPIO[228].
101 MSEO[1] output Nexus message start/end output, alternates eTPU_A[29] and GPIO[225].
102 VDDEH7 power_in I/O supply input for the VDDEH7 segment, 3.3 V to 5.0 V; must be 5 V if JTAG or Nexus is used.
103 EVTI input Nexus event input read at RESET negation to enable the Nexus port, alternates eTPU_A[2] and GPIO[231].
104 VSS power_in Ground.
105 TCK input JTAG test clock input, weak pull-down after reset.
106 EVTO output Nexus event output, alternates eTPU_A[4] and GPIO[227].
107 TDI input JTAG serial test data input, alternates eMIOS[5] and GPIO[232].
108 TMS input JTAG test mode select input, weak pull-up after reset.
109 MSEO[0] output Nexus message start/end output, alternates eTPU_A[27] and GPIO[224].
110 MDO[0] output Nexus message data output 0, alternates eTPU_A[13] and GPIO[220].
111 MDO[1] output Nexus message data output 1, alternates eTPU_A[19] and GPIO[221].
112 MDO[2] output Nexus message data output 2, alternates eTPU_A[21] and GPIO[222].
113 VDDEH7 power_in I/O supply input for the VDDEH7 segment, 3.3 V to 5.0 V; must be 5 V if JTAG or Nexus is used.
114 MDO[3] output Nexus message data output 3, alternates eTPU_A[25] and GPIO[223].
115 VSS power_in Ground.
116 AN[15] input Single-ended analog input AN[15], alternates FCK (eQADC free running clock) and ETPU_A[29]; powered from VDDEH7.
117 AN[14] input Single-ended analog input AN[14], alternates MA[2], ETPU_A[27] and SDI (eQADC serial data in); powered from VDDEH7.
118 AN[13] input Single-ended analog input AN[13], alternates MA[1], ETPU_A[21] and SDO (eQADC serial data out); powered from VDDEH7.
119 AN[12] input Single-ended analog input AN[12], alternates MA[0], ETPU_A[19] and SDS (eQADC serial data strobe); powered from VDDEH7.
120 VDD power_in Internal logic supply input, 1.2 V.
121 AN[35] input Single-ended analog input to the eQADC, powered from VDDA.
122 AN[34] input Single-ended analog input to the eQADC, powered from VDDA.
123 AN[33] input Single-ended analog input to the eQADC, powered from VDDA.
124 AN[32] input Single-ended analog input to the eQADC, powered from VDDA.
125 AN[31] input Single-ended analog input to the eQADC, powered from VDDA.
126 AN[30] input Single-ended analog input to the eQADC, powered from VDDA.
127 AN[28] input Single-ended analog input to the eQADC, powered from VDDA.
128 AN[27] input Single-ended analog input to the eQADC, powered from VDDA.
129 AN[25] input Single-ended analog input to the eQADC, powered from VDDA.
130 AN[24] input Single-ended analog input to the eQADC, powered from VDDA.
131 AN[23] input Single-ended analog input to the eQADC, powered from VDDA.
132 AN[22] input Single-ended analog input to the eQADC, powered from VDDA.
133 VRL input eQADC voltage reference low input.
134 VRH input eQADC voltage reference high input.
135 REFBYPC passive eQADC reference bypass capacitor input.
136 AN[7] input Single-ended analog input AN[7], also negative terminal of differential input DAN3-.
137 AN[6] input Single-ended analog input AN[6], also positive terminal of differential input DAN3+.
138 AN[5] input Single-ended analog input AN[5], also negative terminal of differential input DAN2-.
139 AN[4] input Single-ended analog input AN[4], also positive terminal of differential input DAN2+.
140 AN[3] input Single-ended analog input AN[3], also negative terminal of differential input DAN1-.
141 AN[2] input Single-ended analog input AN[2], also positive terminal of differential input DAN1+.
142 AN[1] input Single-ended analog input AN[1], also negative terminal of differential input DAN0-.
143 AN[0] input Single-ended analog input AN[0], also positive terminal of differential input DAN0+.
144 AN[21] input Single-ended analog input to the eQADC, powered from VDDA.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

CAD (KiCad official)

  • Symbol: SPC563M64L5COAY
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: spc563m64l5coay-etched.step / spc563m64l5coay-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); spc563m64l5coay.step / spc563m64l5coay.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (128 pp, sha256 495db481732ed0ef, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF