Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	4h ago
viewers	spc560p50l5cefar: viewers · Ray	4h ago
package.json	Publish 0.1.0 · Ray	4h ago
page.json	Set visibility: public · Ray	4h ago
README.md	Initial commit: component/spc560p50l5cefar · Ray	4h ago
spc560p50l5cefar-etched.glb	spc560p50l5cefar: factory component page (tier=lcsc) · Ray	4h ago
spc560p50l5cefar-etched.step	spc560p50l5cefar: factory component page (tier=lcsc) · Ray	4h ago
spc560p50l5cefar-hero.glb	Publish 0.1.0 · Ray	4h ago
spc560p50l5cefar-hero.overlay.json	Publish 0.1.0 · Ray	4h ago
spc560p50l5cefar.glb	Publish 0.1.0 · Ray	4h ago
spc560p50l5cefar.kicad_mod	Publish 0.1.0 · Ray	4h ago
spc560p50l5cefar.kicad_sym	Publish 0.1.0 · Ray	4h ago
spc560p50l5cefar.lbr	Publish 0.1.0 · Ray	4h ago
spc560p50l5cefar.step	Publish 0.1.0 · Ray	4h ago

SPC560P50L5CEFAR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

SPC560P50L5CEFAR from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NMI	input	Non-Maskable Interrupt input signal
2	A[6]	bidirectional	Port A pin 6, programmable as GPIO I/O, DSPI_1 clock output, or external interrupt input
3	D[1]	bidirectional	Port D pin 1, programmable as GPIO I/O, eTimer input, or FlexRay receive input
4	F[4]	output	Port F pin 4, programmable as GPIO output or NEXUS Message Data Output line 3
5	F[5]	output	Port F pin 5, programmable as GPIO output or NEXUS Message Data Output line 2
6	VDD_HV_IO0	power_in	3.3 V or 5.0 V input/output supply voltage for I/O power domain 0
7	VSS_HV_IO0	power_in	I/O ground reference for power domain 0
8	F[6]	output	Port F pin 6, programmable as GPIO output or NEXUS Message Data Output line 1
9	MDO[0]	output	NEXUS Message Data Output line 0 signal
10	A[7]	bidirectional	Port A pin 7, programmable as GPIO I/O or DSPI_1 serial output
11	C[4]	bidirectional	Port C pin 4, programmable as GPIO I/O, DSPI_0 chip select, FlexPWM output, or external interrupt input
12	A[8]	input	Port A pin 8, programmable as GPIO I/O or DSPI_1 serial input
13	C[5]	bidirectional	Port C pin 5, programmable as GPIO I/O, DSPI_0 clock, FlexPWM output, or external interrupt input
14	A[5]	bidirectional	Port A pin 5, programmable as GPIO I/O, DSPI_1 or DSPI_0 chip select, eTimer input, or external interrupt input
15	C[7]	bidirectional	Port C pin 7, programmable as GPIO I/O, FlexPWM output, or DSPI_0 serial input
16	C[3]	bidirectional	Port C pin 3, programmable as GPIO I/O, DSPI_0 chip select, eTimer input/output, LIN transmit, or external interrupt input
17	VSS_LV_COR0	power_in	1.2 V core logic decoupling ground; decoupling capacitor required between this pin and VDD_LV_COR0
18	VDD_LV_COR0	power_in	1.2 V core logic decoupling supply; decoupling capacitor required between this pin and VSS_LV_COR0
19	F[7]	output	Port F pin 7, programmable as GPIO output or NEXUS master clock output
20	F[8]	output	Port F pin 8, programmable as GPIO output or NEXUS master serial event output
21	VDD_HV_IO1	power_in	3.3 V or 5.0 V input/output supply voltage for I/O power domain 1
22	VSS_HV_IO1	power_in	I/O ground reference for power domain 1
23	F[9]	output	Port F pin 9, programmable as GPIO output or NEXUS master serial event output
24	F[10]	output	Port F pin 10, programmable as GPIO output or NEXUS event trigger output
25	F[11]	bidirectional	Port F pin 11, programmable as GPIO I/O or NEXUS event trigger input
26	D[9]	bidirectional	Port D pin 9, programmable as GPIO I/O, FlexPWM channel output, or LIN transmit output
27	VDD_HV_OSC	power_in	3.3 V or 5.0 V crystal oscillator amplifier supply voltage
28	VSS_HV_OSC	power_in	Crystal oscillator amplifier ground reference
29	XTAL	passive	Analog output of oscillator amplifier circuit; must be grounded if oscillator is used in bypass mode
30	EXTAL	input	Analog input for oscillator amplifier circuit or clock generator when in bypass mode
31	RESET	bidirectional	Bidirectional reset pin with Schmitt trigger characteristics and noise filter capability
32	D[8]	bidirectional	Port D pin 8, programmable as GPIO I/O, DSPI_1 chip select, or FlexPWM output
33	D[5]	bidirectional	Port D pin 5, programmable as GPIO I/O, DSPI_0 chip select 3, FCU output, or DSPI_3 output
34	D[6]	bidirectional	Port D pin 6, programmable as GPIO I/O, DSPI_0 chip select 2, or DSPI_3 clock input
35	VSS_LV_COR3	power_in	1.2 V PLL module decoupling ground; decoupling capacitor required between this pin and VDD_LV_COR3
36	VDD_LV_COR3	power_in	1.2 V PLL module decoupling supply; decoupling capacitor required between this pin and VSS_LV_COR3
37	D[7]	bidirectional	Port D pin 7, programmable as GPIO I/O, DSPI_1 chip select 3, FCU output, or DSPI_0/DSPI_3 serial input
38	G[0]	output	Port G pin 0, programmable as GPIO I/O or FCU output
39	E[1]	input	Port E pin 1, ADC_0 analog input channel AN[4] for 10-bit analog-to-digital conversion
40	E[3]	input	Port E pin 3, ADC_0 analog input channel AN[6] for 10-bit analog-to-digital conversion
41	C[1]	input	Port C pin 1, ADC_0 analog input channel AN[2] for 10-bit analog-to-digital conversion
42	E[4]	input	Port E pin 4, ADC_0 analog input channel AN[7] for 10-bit analog-to-digital conversion
43	B[7]	input	Port B pin 7, ADC_0 analog input channel AN[0] or LIN_0 receive input
44	E[5]	input	Port E pin 5, ADC_0 analog input channel AN[8] for 10-bit analog-to-digital conversion
45	C[2]	input	Port C pin 2, ADC_0 analog input channel AN[3] for 10-bit analog-to-digital conversion
46	E[6]	input	Port E pin 6, ADC_0 analog input channel AN[9] for 10-bit analog-to-digital conversion
47	B[8]	input	Port B pin 8, ADC_0 analog input channel AN[1] or eTimer input
48	E[7]	input	Port E pin 7, ADC_0 analog input channel AN[10] for 10-bit analog-to-digital conversion
49	E[2]	input	Port E pin 2, ADC_0 analog input channel AN[5] for 10-bit analog-to-digital conversion
50	VDD_HV_ADC0	power_in	ADC_0 supply voltage and high reference voltage for 10-bit analog-to-digital converter
51	VSS_HV_ADC0	power_in	ADC_0 ground and low reference voltage for 10-bit analog-to-digital converter
52	B[9]	input	Port B pin 9, shared ADC_0 and ADC_1 analog input channel AN[11] for conversion
53	B[10]	input	Port B pin 10, shared ADC_0 and ADC_1 analog input channel AN[12] for conversion
54	B[11]	input	Port B pin 11, shared ADC_0 and ADC_1 analog input channel AN[13] for conversion
55	B[12]	input	Port B pin 12, shared ADC_0 and ADC_1 analog input channel AN[14] for conversion
56	VDD_HV_ADC1	power_in	ADC_1 supply voltage and high reference voltage for 10-bit analog-to-digital converter
57	VSS_HV_ADC1	power_in	ADC_1 ground and low reference voltage for 10-bit analog-to-digital converter
58	D[15]	input	Port D pin 15, ADC_1 analog input channel AN[4] for 10-bit analog-to-digital conversion
59	E[8]	input	Port E pin 8, ADC_1 analog input channel AN[6] for 10-bit analog-to-digital conversion
60	B[13]	input	Port B pin 13, ADC_1 analog input channel AN[0] or LIN_1 receive input
61	E[9]	input	Port E pin 9, ADC_1 analog input channel AN[7] for 10-bit analog-to-digital conversion
62	B[15]	input	Port B pin 15, ADC_1 analog input channel AN[2] for 10-bit analog-to-digital conversion
63	E[10]	input	Port E pin 10, ADC_1 analog input channel AN[8] for 10-bit analog-to-digital conversion
64	B[14]	input	Port B pin 14, ADC_1 analog input channel AN[1] or eTimer input
65	E[11]	input	Port E pin 11, ADC_1 analog input channel AN[9] for 10-bit analog-to-digital conversion
66	C[0]	input	Port C pin 0, ADC_1 analog input channel AN[3] for 10-bit analog-to-digital conversion
67	E[12]	input	Port E pin 12, ADC_1 analog input channel AN[10] for 10-bit analog-to-digital conversion
68	E[0]	input	Port E pin 0, ADC_1 analog input channel AN[5] for 10-bit analog-to-digital conversion
69	BCTRL	bidirectional	Voltage regulator external NPN ballast transistor base control pin for on-chip regulator
70	VDD_LV_REGCOR	power_in	1.2 V decoupling supply for core logic and regulator feedback; decoupling capacitor required
71	VSS_LV_REGCOR	power_in	1.2 V decoupling ground for core logic and regulator feedback; decoupling capacitor required
72	VDD_HV_REG	power_in	3.3 V or 5.0 V voltage regulator supply voltage input
73	A[0]	bidirectional	Port A pin 0, programmable as GPIO I/O, eTimer input/output, DSPI clock, or external interrupt input
74	A[1]	bidirectional	Port A pin 1, programmable as GPIO I/O, eTimer input/output, DSPI serial output, or external interrupt input
75	G[11]	bidirectional	Port G pin 11, programmable as GPIO I/O or FlexPWM fault input signal
76	D[10]	bidirectional	Port D pin 10, programmable as GPIO I/O, FlexPWM output, or DSPI chip select/clock
77	G[10]	bidirectional	Port G pin 10, programmable as GPIO I/O or FlexPWM fault input signal
78	D[11]	bidirectional	Port D pin 11, programmable as GPIO I/O, FlexPWM output, or DSPI serial input/clock
79	G[9]	bidirectional	Port G pin 9, programmable as GPIO I/O or FlexPWM fault input signal
80	C[11]	bidirectional	Port C pin 11, programmable as GPIO I/O, eTimer input/output, or DSPI chip select/output
81	G[8]	bidirectional	Port G pin 8, programmable as GPIO I/O or FlexPWM fault input signal
82	C[12]	bidirectional	Port C pin 12, programmable as GPIO I/O, eTimer input/output, or DSPI output/input
83	G[7]	output	Port G pin 7, programmable as GPIO I/O or FlexPWM output
84	A[2]	bidirectional	Port A pin 2, programmable as GPIO I/O, eTimer input/output, FlexPWM output, or external interrupt input
85	G[5]	bidirectional	Port G pin 5, programmable as GPIO I/O or FlexPWM channel input
86	TDI	input	Test Data Input for JTAG 1149.1 boundary scan operations
87	TMS	bidirectional	JTAG Test Mode Select and state machine control signal
88	TCK	input	JTAG test clock input for IEEE 1149.1 Test Access Port
89	TDO	output	Test Data Output from JTAG 1149.1 boundary scan register
90	VSS_HV_IO2	power_in	I/O ground reference for power domain 2
91	VDD_HV_IO2	power_in	3.3 V or 5.0 V input/output supply voltage for I/O power domain 2
92	A[3]	bidirectional	Port A pin 3, programmable as GPIO I/O, eTimer input/output, DSPI chip select, or external interrupt input
93	VDD_LV_COR1	power_in	1.2 V core logic decoupling supply; decoupling capacitor required between this pin and VSS_LV_COR1
94	VSS_LV_COR1	power_in	1.2 V core logic decoupling ground; decoupling capacitor required between this pin and VDD_LV_COR1
95	D[13]	bidirectional	Port D pin 13, programmable as GPIO I/O, FlexPWM output, or DSPI serial output
96	VSS_HV_FL	power_in	Code and data flash module ground reference
97	VDD_HV_FL	power_in	Code and data flash module supply voltage
98	G[6]	output	Port G pin 6, programmable as GPIO I/O or FlexPWM output
99	D[12]	bidirectional	Port D pin 12, programmable as GPIO I/O or FlexPWM channel output
100	G[4]	output	Port G pin 4, programmable as GPIO I/O or FlexPWM output
101	C[13]	bidirectional	Port C pin 13, programmable as GPIO I/O, eTimer input/output, or FlexPWM synchronization input
102	G[2]	bidirectional	Port G pin 2, programmable as GPIO I/O or FlexPWM channel input
103	C[14]	bidirectional	Port C pin 14, programmable as GPIO I/O, eTimer input/output, or CTU trigger input
104	G[3]	output	Port G pin 3, programmable as GPIO I/O or FlexPWM output
105	D[14]	bidirectional	Port D pin 14, programmable as GPIO I/O, FlexPWM output, or DSPI serial output
106	F[12]	bidirectional	Port F pin 12, programmable as GPIO I/O or eTimer input/output
107	VPP_TEST	power_in	Test pin for factory testing purposes only; must be tied to ground VSS in normal operating mode
108	A[4]	bidirectional	Port A pin 4, programmable as GPIO I/O, eTimer input/output, DSPI chip select, or external interrupt input
109	B[0]	bidirectional	Port B pin 0, programmable as GPIO I/O, FlexCAN transmit output, eTimer input/output, or external interrupt input
110	B[1]	bidirectional	Port B pin 1, programmable as GPIO I/O, FlexCAN receive input, or eTimer input/output
111	C[10]	bidirectional	Port C pin 10, programmable as GPIO I/O, DSPI chip select 2, or FlexPWM output
112	F[13]	bidirectional	Port F pin 13, programmable as GPIO I/O or eTimer input/output
113	F[15]	bidirectional	Port F pin 15, programmable as GPIO I/O or LIN_1 receive input
114	B[2]	bidirectional	Port B pin 2, programmable as GPIO I/O or LIN_0 transmit output
115	F[14]	bidirectional	Port F pin 14, programmable as GPIO I/O or LIN_1 transmit output
116	B[3]	bidirectional	Port B pin 3, programmable as GPIO I/O or LIN_0 receive input
117	E[13]	bidirectional	Port E pin 13, programmable as GPIO I/O, DSPI clock input/output, or external interrupt input
118	A[10]	bidirectional	Port A pin 10, programmable as GPIO I/O, DSPI chip select 0, FlexPWM output, or external interrupt input
119	E[14]	bidirectional	Port E pin 14, programmable as GPIO I/O, DSPI serial output, or external interrupt input
120	A[11]	bidirectional	Port A pin 11, programmable as GPIO I/O, DSPI clock output, FlexPWM output, or external interrupt input
121	E[15]	bidirectional	Port E pin 15, programmable as GPIO I/O, DSPI serial input, or external interrupt input
122	A[12]	bidirectional	Port A pin 12, programmable as GPIO I/O, DSPI serial output, FlexPWM output, or external interrupt input
123	C[9]	bidirectional	Port C pin 9, programmable as GPIO I/O, DSPI chip select 3, or FlexPWM channel input/output
124	C[15]	bidirectional	Port C pin 15, programmable as GPIO I/O, FlexRay enable output, eTimer input/output, or FlexPWM output/sync input
125	D[0]	bidirectional	Port D pin 0, programmable as GPIO I/O, FlexRay transmit output, eTimer input/output, or FlexPWM output
126	VDD_HV_IO3	power_in	3.3 V or 5.0 V input/output supply voltage for I/O power domain 3
127	VSS_HV_IO3	power_in	I/O ground reference for power domain 3
128	D[3]	bidirectional	Port D pin 3, programmable as GPIO I/O, FlexRay transmit output, eTimer input/output, or FlexPWM output
129	D[4]	bidirectional	Port D pin 4, programmable as GPIO I/O, FlexRay enable output, eTimer input/output, or FlexPWM output
130	C[8]	bidirectional	Port C pin 8, programmable as GPIO I/O, DSPI chip select 1, or FlexPWM output
131	VDD_LV_COR2	power_in	1.2 V core logic decoupling supply; decoupling capacitor required between this pin and VSS_LV_COR2
132	VSS_LV_COR2	power_in	1.2 V core logic decoupling ground; decoupling capacitor required between this pin and VDD_LV_COR2
133	F[0]	bidirectional	Port F pin 0, programmable as GPIO I/O, FlexRay debug output, or DSPI chip select 3
134	A[9]	bidirectional	Port A pin 9, programmable as GPIO I/O, DSPI chip select 1, FlexPWM output, or fault input
135	F[1]	bidirectional	Port F pin 1, programmable as GPIO I/O, FlexRay debug output, or DSPI chip select 2
136	A[13]	bidirectional	Port A pin 13, programmable as GPIO I/O, DSPI serial input, FlexPWM output, or external interrupt input
137	F[2]	bidirectional	Port F pin 2, programmable as GPIO I/O, FlexRay debug output, or DSPI chip select 1
138	B[6]	bidirectional	Port B pin 6, programmable as GPIO I/O, clock output, DSPI chip select 2, or external interrupt input
139	F[3]	bidirectional	Port F pin 3, programmable as GPIO I/O, FlexRay chip select output, or DSPI serial input
140	D[2]	bidirectional	Port D pin 2, programmable as GPIO I/O, eTimer input/output, FlexPWM channel input, or FlexRay receive input
141	G[1]	output	Port G pin 1, programmable as GPIO I/O or FCU output
142	C[6]	bidirectional	Port C pin 6, programmable as GPIO I/O, DSPI serial output, FlexPWM output, or external interrupt input
143	A[14]	bidirectional	Port A pin 14, programmable as GPIO I/O, Safety Port transmit output, eTimer input/output, or external interrupt input
144	A[15]	bidirectional	Port A pin 15, programmable as GPIO I/O, Safety Port receive input, eTimer input/output, or external interrupt input

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-144(20x20)
Category	Embedded Processors & Controllers
Pins	144

CAD (KiCad official)

Symbol: SPC560P50L5CEFAR
Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
3D model files: spc560p50l5cefar-etched.step / spc560p50l5cefar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); spc560p50l5cefar.step / spc560p50l5cefar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (112 pp, sha256 d835583856bd2db4, retrieved 2026-10-07, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF