component
SPC560P50L5CEFAR
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+180@@ -0,0 +1,180 @@+# SPC560P50L5CEFAR++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)++SPC560P50L5CEFAR from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NMI | input | Non-Maskable Interrupt input signal |+| 2 | A[6] | bidirectional | Port A pin 6, programmable as GPIO I/O, DSPI_1 clock output, or external interrupt input |+| 3 | D[1] | bidirectional | Port D pin 1, programmable as GPIO I/O, eTimer input, or FlexRay receive input |+| 4 | F[4] | output | Port F pin 4, programmable as GPIO output or NEXUS Message Data Output line 3 |+| 5 | F[5] | output | Port F pin 5, programmable as GPIO output or NEXUS Message Data Output line 2 |+| 6 | VDD_HV_IO0 | power_in | 3.3 V or 5.0 V input/output supply voltage for I/O power domain 0 |+| 7 | VSS_HV_IO0 | power_in | I/O ground reference for power domain 0 |+| 8 | F[6] | output | Port F pin 6, programmable as GPIO output or NEXUS Message Data Output line 1 |+| 9 | MDO[0] | output | NEXUS Message Data Output line 0 signal |+| 10 | A[7] | bidirectional | Port A pin 7, programmable as GPIO I/O or DSPI_1 serial output |+| 11 | C[4] | bidirectional | Port C pin 4, programmable as GPIO I/O, DSPI_0 chip select, FlexPWM output, or external interrupt input |+| 12 | A[8] | input | Port A pin 8, programmable as GPIO I/O or DSPI_1 serial input |+| 13 | C[5] | bidirectional | Port C pin 5, programmable as GPIO I/O, DSPI_0 clock, FlexPWM output, or external interrupt input |+| 14 | A[5] | bidirectional | Port A pin 5, programmable as GPIO I/O, DSPI_1 or DSPI_0 chip select, eTimer input, or external interrupt input |+| 15 | C[7] | bidirectional | Port C pin 7, programmable as GPIO I/O, FlexPWM output, or DSPI_0 serial input |+| 16 | C[3] | bidirectional | Port C pin 3, programmable as GPIO I/O, DSPI_0 chip select, eTimer input/output, LIN transmit, or external interrupt input |+| 17 | VSS_LV_COR0 | power_in | 1.2 V core logic decoupling ground; decoupling capacitor required between this pin and VDD_LV_COR0 |+| 18 | VDD_LV_COR0 | power_in | 1.2 V core logic decoupling supply; decoupling capacitor required between this pin and VSS_LV_COR0 |+| 19 | F[7] | output | Port F pin 7, programmable as GPIO output or NEXUS master clock output |+| 20 | F[8] | output | Port F pin 8, programmable as GPIO output or NEXUS master serial event output |+| 21 | VDD_HV_IO1 | power_in | 3.3 V or 5.0 V input/output supply voltage for I/O power domain 1 |+| 22 | VSS_HV_IO1 | power_in | I/O ground reference for power domain 1 |+| 23 | F[9] | output | Port F pin 9, programmable as GPIO output or NEXUS master serial event output |+| 24 | F[10] | output | Port F pin 10, programmable as GPIO output or NEXUS event trigger output |+| 25 | F[11] | bidirectional | Port F pin 11, programmable as GPIO I/O or NEXUS event trigger input |+| 26 | D[9] | bidirectional | Port D pin 9, programmable as GPIO I/O, FlexPWM channel output, or LIN transmit output |+| 27 | VDD_HV_OSC | power_in | 3.3 V or 5.0 V crystal oscillator amplifier supply voltage |+| 28 | VSS_HV_OSC | power_in | Crystal oscillator amplifier ground reference |+| 29 | XTAL | passive | Analog output of oscillator amplifier circuit; must be grounded if oscillator is used in bypass mode |+| 30 | EXTAL | input | Analog input for oscillator amplifier circuit or clock generator when in bypass mode |+| 31 | RESET | bidirectional | Bidirectional reset pin with Schmitt trigger characteristics and noise filter capability |+| 32 | D[8] | bidirectional | Port D pin 8, programmable as GPIO I/O, DSPI_1 chip select, or FlexPWM output |+| 33 | D[5] | bidirectional | Port D pin 5, programmable as GPIO I/O, DSPI_0 chip select 3, FCU output, or DSPI_3 output |+| 34 | D[6] | bidirectional | Port D pin 6, programmable as GPIO I/O, DSPI_0 chip select 2, or DSPI_3 clock input |+| 35 | VSS_LV_COR3 | power_in | 1.2 V PLL module decoupling ground; decoupling capacitor required between this pin and VDD_LV_COR3 |+| 36 | VDD_LV_COR3 | power_in | 1.2 V PLL module decoupling supply; decoupling capacitor required between this pin and VSS_LV_COR3 |+| 37 | D[7] | bidirectional | Port D pin 7, programmable as GPIO I/O, DSPI_1 chip select 3, FCU output, or DSPI_0/DSPI_3 serial input |+| 38 | G[0] | output | Port G pin 0, programmable as GPIO I/O or FCU output |+| 39 | E[1] | input | Port E pin 1, ADC_0 analog input channel AN[4] for 10-bit analog-to-digital conversion |+| 40 | E[3] | input | Port E pin 3, ADC_0 analog input channel AN[6] for 10-bit analog-to-digital conversion |+| 41 | C[1] | input | Port C pin 1, ADC_0 analog input channel AN[2] for 10-bit analog-to-digital conversion |+| 42 | E[4] | input | Port E pin 4, ADC_0 analog input channel AN[7] for 10-bit analog-to-digital conversion |+| 43 | B[7] | input | Port B pin 7, ADC_0 analog input channel AN[0] or LIN_0 receive input |+| 44 | E[5] | input | Port E pin 5, ADC_0 analog input channel AN[8] for 10-bit analog-to-digital conversion |+| 45 | C[2] | input | Port C pin 2, ADC_0 analog input channel AN[3] for 10-bit analog-to-digital conversion |+| 46 | E[6] | input | Port E pin 6, ADC_0 analog input channel AN[9] for 10-bit analog-to-digital conversion |+| 47 | B[8] | input | Port B pin 8, ADC_0 analog input channel AN[1] or eTimer input |+| 48 | E[7] | input | Port E pin 7, ADC_0 analog input channel AN[10] for 10-bit analog-to-digital conversion |+| 49 | E[2] | input | Port E pin 2, ADC_0 analog input channel AN[5] for 10-bit analog-to-digital conversion |+| 50 | VDD_HV_ADC0 | power_in | ADC_0 supply voltage and high reference voltage for 10-bit analog-to-digital converter |+| 51 | VSS_HV_ADC0 | power_in | ADC_0 ground and low reference voltage for 10-bit analog-to-digital converter |+| 52 | B[9] | input | Port B pin 9, shared ADC_0 and ADC_1 analog input channel AN[11] for conversion |+| 53 | B[10] | input | Port B pin 10, shared ADC_0 and ADC_1 analog input channel AN[12] for conversion |+| 54 | B[11] | input | Port B pin 11, shared ADC_0 and ADC_1 analog input channel AN[13] for conversion |+| 55 | B[12] | input | Port B pin 12, shared ADC_0 and ADC_1 analog input channel AN[14] for conversion |+| 56 | VDD_HV_ADC1 | power_in | ADC_1 supply voltage and high reference voltage for 10-bit analog-to-digital converter |+| 57 | VSS_HV_ADC1 | power_in | ADC_1 ground and low reference voltage for 10-bit analog-to-digital converter |+| 58 | D[15] | input | Port D pin 15, ADC_1 analog input channel AN[4] for 10-bit analog-to-digital conversion |+| 59 | E[8] | input | Port E pin 8, ADC_1 analog input channel AN[6] for 10-bit analog-to-digital conversion |+| 60 | B[13] | input | Port B pin 13, ADC_1 analog input channel AN[0] or LIN_1 receive input |+| 61 | E[9] | input | Port E pin 9, ADC_1 analog input channel AN[7] for 10-bit analog-to-digital conversion |+| 62 | B[15] | input | Port B pin 15, ADC_1 analog input channel AN[2] for 10-bit analog-to-digital conversion |+| 63 | E[10] | input | Port E pin 10, ADC_1 analog input channel AN[8] for 10-bit analog-to-digital conversion |+| 64 | B[14] | input | Port B pin 14, ADC_1 analog input channel AN[1] or eTimer input |+| 65 | E[11] | input | Port E pin 11, ADC_1 analog input channel AN[9] for 10-bit analog-to-digital conversion |+| 66 | C[0] | input | Port C pin 0, ADC_1 analog input channel AN[3] for 10-bit analog-to-digital conversion |+| 67 | E[12] | input | Port E pin 12, ADC_1 analog input channel AN[10] for 10-bit analog-to-digital conversion |+| 68 | E[0] | input | Port E pin 0, ADC_1 analog input channel AN[5] for 10-bit analog-to-digital conversion |+| 69 | BCTRL | bidirectional | Voltage regulator external NPN ballast transistor base control pin for on-chip regulator |+| 70 | VDD_LV_REGCOR | power_in | 1.2 V decoupling supply for core logic and regulator feedback; decoupling capacitor required |+| 71 | VSS_LV_REGCOR | power_in | 1.2 V decoupling ground for core logic and regulator feedback; decoupling capacitor required |+| 72 | VDD_HV_REG | power_in | 3.3 V or 5.0 V voltage regulator supply voltage input |+| 73 | A[0] | bidirectional | Port A pin 0, programmable as GPIO I/O, eTimer input/output, DSPI clock, or external interrupt input |+| 74 | A[1] | bidirectional | Port A pin 1, programmable as GPIO I/O, eTimer input/output, DSPI serial output, or external interrupt input |+| 75 | G[11] | bidirectional | Port G pin 11, programmable as GPIO I/O or FlexPWM fault input signal |+| 76 | D[10] | bidirectional | Port D pin 10, programmable as GPIO I/O, FlexPWM output, or DSPI chip select/clock |+| 77 | G[10] | bidirectional | Port G pin 10, programmable as GPIO I/O or FlexPWM fault input signal |+| 78 | D[11] | bidirectional | Port D pin 11, programmable as GPIO I/O, FlexPWM output, or DSPI serial input/clock |+| 79 | G[9] | bidirectional | Port G pin 9, programmable as GPIO I/O or FlexPWM fault input signal |+| 80 | C[11] | bidirectional | Port C pin 11, programmable as GPIO I/O, eTimer input/output, or DSPI chip select/output |+| 81 | G[8] | bidirectional | Port G pin 8, programmable as GPIO I/O or FlexPWM fault input signal |+| 82 | C[12] | bidirectional | Port C pin 12, programmable as GPIO I/O, eTimer input/output, or DSPI output/input |+| 83 | G[7] | output | Port G pin 7, programmable as GPIO I/O or FlexPWM output |+| 84 | A[2] | bidirectional | Port A pin 2, programmable as GPIO I/O, eTimer input/output, FlexPWM output, or external interrupt input |+| 85 | G[5] | bidirectional | Port G pin 5, programmable as GPIO I/O or FlexPWM channel input |+| 86 | TDI | input | Test Data Input for JTAG 1149.1 boundary scan operations |+| 87 | TMS | bidirectional | JTAG Test Mode Select and state machine control signal |+| 88 | TCK | input | JTAG test clock input for IEEE 1149.1 Test Access Port |+| 89 | TDO | output | Test Data Output from JTAG 1149.1 boundary scan register |+| 90 | VSS_HV_IO2 | power_in | I/O ground reference for power domain 2 |+| 91 | VDD_HV_IO2 | power_in | 3.3 V or 5.0 V input/output supply voltage for I/O power domain 2 |+| 92 | A[3] | bidirectional | Port A pin 3, programmable as GPIO I/O, eTimer input/output, DSPI chip select, or external interrupt input |+| 93 | VDD_LV_COR1 | power_in | 1.2 V core logic decoupling supply; decoupling capacitor required between this pin and VSS_LV_COR1 |+| 94 | VSS_LV_COR1 | power_in | 1.2 V core logic decoupling ground; decoupling capacitor required between this pin and VDD_LV_COR1 |+| 95 | D[13] | bidirectional | Port D pin 13, programmable as GPIO I/O, FlexPWM output, or DSPI serial output |+| 96 | VSS_HV_FL | power_in | Code and data flash module ground reference |+| 97 | VDD_HV_FL | power_in | Code and data flash module supply voltage |+| 98 | G[6] | output | Port G pin 6, programmable as GPIO I/O or FlexPWM output |+| 99 | D[12] | bidirectional | Port D pin 12, programmable as GPIO I/O or FlexPWM channel output |+| 100 | G[4] | output | Port G pin 4, programmable as GPIO I/O or FlexPWM output |+| 101 | C[13] | bidirectional | Port C pin 13, programmable as GPIO I/O, eTimer input/output, or FlexPWM synchronization input |+| 102 | G[2] | bidirectional | Port G pin 2, programmable as GPIO I/O or FlexPWM channel input |+| 103 | C[14] | bidirectional | Port C pin 14, programmable as GPIO I/O, eTimer input/output, or CTU trigger input |+| 104 | G[3] | output | Port G pin 3, programmable as GPIO I/O or FlexPWM output |+| 105 | D[14] | bidirectional | Port D pin 14, programmable as GPIO I/O, FlexPWM output, or DSPI serial output |+| 106 | F[12] | bidirectional | Port F pin 12, programmable as GPIO I/O or eTimer input/output |+| 107 | VPP_TEST | power_in | Test pin for factory testing purposes only; must be tied to ground VSS in normal operating mode |+| 108 | A[4] | bidirectional | Port A pin 4, programmable as GPIO I/O, eTimer input/output, DSPI chip select, or external interrupt input |+| 109 | B[0] | bidirectional | Port B pin 0, programmable as GPIO I/O, FlexCAN transmit output, eTimer input/output, or external interrupt input |+| 110 | B[1] | bidirectional | Port B pin 1, programmable as GPIO I/O, FlexCAN receive input, or eTimer input/output |+| 111 | C[10] | bidirectional | Port C pin 10, programmable as GPIO I/O, DSPI chip select 2, or FlexPWM output |+| 112 | F[13] | bidirectional | Port F pin 13, programmable as GPIO I/O or eTimer input/output |+| 113 | F[15] | bidirectional | Port F pin 15, programmable as GPIO I/O or LIN_1 receive input |+| 114 | B[2] | bidirectional | Port B pin 2, programmable as GPIO I/O or LIN_0 transmit output |+| 115 | F[14] | bidirectional | Port F pin 14, programmable as GPIO I/O or LIN_1 transmit output |+| 116 | B[3] | bidirectional | Port B pin 3, programmable as GPIO I/O or LIN_0 receive input |+| 117 | E[13] | bidirectional | Port E pin 13, programmable as GPIO I/O, DSPI clock input/output, or external interrupt input |+| 118 | A[10] | bidirectional | Port A pin 10, programmable as GPIO I/O, DSPI chip select 0, FlexPWM output, or external interrupt input |+| 119 | E[14] | bidirectional | Port E pin 14, programmable as GPIO I/O, DSPI serial output, or external interrupt input |+| 120 | A[11] | bidirectional | Port A pin 11, programmable as GPIO I/O, DSPI clock output, FlexPWM output, or external interrupt input |+| 121 | E[15] | bidirectional | Port E pin 15, programmable as GPIO I/O, DSPI serial input, or external interrupt input |+| 122 | A[12] | bidirectional | Port A pin 12, programmable as GPIO I/O, DSPI serial output, FlexPWM output, or external interrupt input |+| 123 | C[9] | bidirectional | Port C pin 9, programmable as GPIO I/O, DSPI chip select 3, or FlexPWM channel input/output |+| 124 | C[15] | bidirectional | Port C pin 15, programmable as GPIO I/O, FlexRay enable output, eTimer input/output, or FlexPWM output/sync input |+| 125 | D[0] | bidirectional | Port D pin 0, programmable as GPIO I/O, FlexRay transmit output, eTimer input/output, or FlexPWM output |+| 126 | VDD_HV_IO3 | power_in | 3.3 V or 5.0 V input/output supply voltage for I/O power domain 3 |+| 127 | VSS_HV_IO3 | power_in | I/O ground reference for power domain 3 |+| 128 | D[3] | bidirectional | Port D pin 3, programmable as GPIO I/O, FlexRay transmit output, eTimer input/output, or FlexPWM output |+| 129 | D[4] | bidirectional | Port D pin 4, programmable as GPIO I/O, FlexRay enable output, eTimer input/output, or FlexPWM output |+| 130 | C[8] | bidirectional | Port C pin 8, programmable as GPIO I/O, DSPI chip select 1, or FlexPWM output |+| 131 | VDD_LV_COR2 | power_in | 1.2 V core logic decoupling supply; decoupling capacitor required between this pin and VSS_LV_COR2 |+| 132 | VSS_LV_COR2 | power_in | 1.2 V core logic decoupling ground; decoupling capacitor required between this pin and VDD_LV_COR2 |+| 133 | F[0] | bidirectional | Port F pin 0, programmable as GPIO I/O, FlexRay debug output, or DSPI chip select 3 |+| 134 | A[9] | bidirectional | Port A pin 9, programmable as GPIO I/O, DSPI chip select 1, FlexPWM output, or fault input |+| 135 | F[1] | bidirectional | Port F pin 1, programmable as GPIO I/O, FlexRay debug output, or DSPI chip select 2 |+| 136 | A[13] | bidirectional | Port A pin 13, programmable as GPIO I/O, DSPI serial input, FlexPWM output, or external interrupt input |+| 137 | F[2] | bidirectional | Port F pin 2, programmable as GPIO I/O, FlexRay debug output, or DSPI chip select 1 |+| 138 | B[6] | bidirectional | Port B pin 6, programmable as GPIO I/O, clock output, DSPI chip select 2, or external interrupt input |+| 139 | F[3] | bidirectional | Port F pin 3, programmable as GPIO I/O, FlexRay chip select output, or DSPI serial input |+| 140 | D[2] | bidirectional | Port D pin 2, programmable as GPIO I/O, eTimer input/output, FlexPWM channel input, or FlexRay receive input |+| 141 | G[1] | output | Port G pin 1, programmable as GPIO I/O or FCU output |+| 142 | C[6] | bidirectional | Port C pin 6, programmable as GPIO I/O, DSPI serial output, FlexPWM output, or external interrupt input |+| 143 | A[14] | bidirectional | Port A pin 14, programmable as GPIO I/O, Safety Port transmit output, eTimer input/output, or external interrupt input |+| 144 | A[15] | bidirectional | Port A pin 15, programmable as GPIO I/O, Safety Port receive input, eTimer input/output, or external interrupt input |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-144(20x20) |+| Category | Embedded Processors & Controllers |+| Pins | 144 |++## CAD (KiCad official)++- Symbol: `SPC560P50L5CEFAR`+- Footprint: `Package_QFP:LQFP-144_20x20mm_P0.5mm`+- 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)+- 3D model files: `spc560p50l5cefar-etched.step` / `spc560p50l5cefar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `spc560p50l5cefar.step` / `spc560p50l5cefar.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588942362793398272) (112 pp, sha256 `d835583856bd2db4`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/spc560p50l5cefar-datasheet.pdf)
page.jsonadded+1016@@ -0,0 +1,1016 @@+{+ "slug": "spc560p50l5cefar",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "spc560p50l5cefar",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "spc560p50l5cefar.kicad_sym",+ "spc560p50l5cefar.kicad_mod",+ "spc560p50l5cefar.glb",+ "spc560p50l5cefar.step",+ "spc560p50l5cefar.lbr",+ "docs/hero.png",+ "docs/spc560p50l5cefar-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "spc560p50l5cefar-hero.glb",+ "spc560p50l5cefar-hero.overlay.json"+ ],+ "component": {+ "mpn": "SPC560P50L5CEFAR",+ "manufacturer": "STMicroelectronics",+ "package": "LQFP-144(20x20)",+ "pin_count": 144,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588942362793398272",+ "parts": {+ "symbol": "spc560p50l5cefar.kicad_sym",+ "footprint": "spc560p50l5cefar.kicad_mod",+ "model_3d": "spc560p50l5cefar-hero.glb",+ "model_3d_plain": "spc560p50l5cefar.glb",+ "model_3d_step": "spc560p50l5cefar-etched.step",+ "model_3d_step_plain": "spc560p50l5cefar.step",+ "lbr": "spc560p50l5cefar.lbr"+ },+ "distributor_links": {+ "lcsc": "C2053989",+ "digikey": "497-11616-2-ND",+ "mouser": "511-SPC560P50L5CEFAR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T07:52:12Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-11616-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "511-SPC560P50L5CEFAR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "NMI",+ "type": "input",+ "description": "Non-Maskable Interrupt input signal"+ },+ {+ "number": "2",+ "name": "A[6]",+ "type": "bidirectional",+ "description": "Port A pin 6, programmable as GPIO I/O, DSPI_1 clock output, or external interrupt input"+ },+ {+ "number": "3",+ "name": "D[1]",+ "type": "bidirectional",+ "description": "Port D pin 1, programmable as GPIO I/O, eTimer input, or FlexRay receive input"+ },+ {+ "number": "4",+ "name": "F[4]",+ "type": "output",+ "description": "Port F pin 4, programmable as GPIO output or NEXUS Message Data Output line 3"+ },+ {+ "number": "5",+ "name": "F[5]",+ "type": "output",+ "description": "Port F pin 5, programmable as GPIO output or NEXUS Message Data Output line 2"+ },+ {+ "number": "6",+ "name": "VDD_HV_IO0",+ "type": "power_in",+ "description": "3.3 V or 5.0 V input/output supply voltage for I/O power domain 0"+ },+ {+ "number": "7",+ "name": "VSS_HV_IO0",+ "type": "power_in",+ "description": "I/O ground reference for power domain 0"+ },+ {+ "number": "8",+ "name": "F[6]",+ "type": "output",+ "description": "Port F pin 6, programmable as GPIO output or NEXUS Message Data Output line 1"+ },+ {+ "number": "9",+ "name": "MDO[0]",+ "type": "output",+ "description": "NEXUS Message Data Output line 0 signal"+ },+ {+ "number": "10",+ "name": "A[7]",+ "type": "bidirectional",+ "description": "Port A pin 7, programmable as GPIO I/O or DSPI_1 serial output"+ },+ {+ "number": "11",+ "name": "C[4]",+ "type": "bidirectional",+ "description": "Port C pin 4, programmable as GPIO I/O, DSPI_0 chip select, FlexPWM output, or external interrupt input"+ },+ {+ "number": "12",+ "name": "A[8]",+ "type": "input",+ "description": "Port A pin 8, programmable as GPIO I/O or DSPI_1 serial input"+ },+ {+ "number": "13",+ "name": "C[5]",+ "type": "bidirectional",+ "description": "Port C pin 5, programmable as GPIO I/O, DSPI_0 clock, FlexPWM output, or external interrupt input"+ },+ {+ "number": "14",+ "name": "A[5]",+ "type": "bidirectional",+ "description": "Port A pin 5, programmable as GPIO I/O, DSPI_1 or DSPI_0 chip select, eTimer input, or external interrupt input"+ },+ {+ "number": "15",+ "name": "C[7]",+ "type": "bidirectional",+ "description": "Port C pin 7, programmable as GPIO I/O, FlexPWM output, or DSPI_0 serial input"+ },+ {+ "number": "16",+ "name": "C[3]",+ "type": "bidirectional",+ "description": "Port C pin 3, programmable as GPIO I/O, DSPI_0 chip select, eTimer input/output, LIN transmit, or external interrupt input"+ },+ {+ "number": "17",+ "name": "VSS_LV_COR0",+ "type": "power_in",+ "description": "1.2 V core logic decoupling ground; decoupling capacitor required between this pin and VDD_LV_COR0"+ },+ {+ "number": "18",+ "name": "VDD_LV_COR0",+ "type": "power_in",+ "description": "1.2 V core logic decoupling supply; decoupling capacitor required between this pin and VSS_LV_COR0"+ },+ {+ "number": "19",+ "name": "F[7]",+ "type": "output",+ "description": "Port F pin 7, programmable as GPIO output or NEXUS master clock output"+ },+ {+ "number": "20",+ "name": "F[8]",+ "type": "output",+ "description": "Port F pin 8, programmable as GPIO output or NEXUS master serial event output"+ },+ {+ "number": "21",+ "name": "VDD_HV_IO1",+ "type": "power_in",+ "description": "3.3 V or 5.0 V input/output supply voltage for I/O power domain 1"+ },+ {+ "number": "22",+ "name": "VSS_HV_IO1",+ "type": "power_in",+ "description": "I/O ground reference for power domain 1"+ },+ {+ "number": "23",+ "name": "F[9]",+ "type": "output",+ "description": "Port F pin 9, programmable as GPIO output or NEXUS master serial event output"+ },+ {+ "number": "24",+ "name": "F[10]",+ "type": "output",+ "description": "Port F pin 10, programmable as GPIO output or NEXUS event trigger output"+ },+ {+ "number": "25",+ "name": "F[11]",+ "type": "bidirectional",+ "description": "Port F pin 11, programmable as GPIO I/O or NEXUS event trigger input"+ },+ {+ "number": "26",+ "name": "D[9]",+ "type": "bidirectional",+ "description": "Port D pin 9, programmable as GPIO I/O, FlexPWM channel output, or LIN transmit output"+ },+ {+ "number": "27",+ "name": "VDD_HV_OSC",+ "type": "power_in",+ "description": "3.3 V or 5.0 V crystal oscillator amplifier supply voltage"+ },+ {+ "number": "28",+ "name": "VSS_HV_OSC",+ "type": "power_in",+ "description": "Crystal oscillator amplifier ground reference"+ },+ {+ "number": "29",+ "name": "XTAL",+ "type": "passive",+ "description": "Analog output of oscillator amplifier circuit; must be grounded if oscillator is used in bypass mode"+ },+ {+ "number": "30",+ "name": "EXTAL",+ "type": "input",+ "description": "Analog input for oscillator amplifier circuit or clock generator when in bypass mode"+ },+ {+ "number": "31",+ "name": "RESET",+ "type": "bidirectional",+ "description": "Bidirectional reset pin with Schmitt trigger characteristics and noise filter capability"+ },+ {+ "number": "32",+ "name": "D[8]",+ "type": "bidirectional",+ "description": "Port D pin 8, programmable as GPIO I/O, DSPI_1 chip select, or FlexPWM output"+ },+ {+ "number": "33",+ "name": "D[5]",+ "type": "bidirectional",+ "description": "Port D pin 5, programmable as GPIO I/O, DSPI_0 chip select 3, FCU output, or DSPI_3 output"+ },+ {+ "number": "34",+ "name": "D[6]",+ "type": "bidirectional",+ "description": "Port D pin 6, programmable as GPIO I/O, DSPI_0 chip select 2, or DSPI_3 clock input"+ },+ {+ "number": "35",+ "name": "VSS_LV_COR3",+ "type": "power_in",+ "description": "1.2 V PLL module decoupling ground; decoupling capacitor required between this pin and VDD_LV_COR3"+ },+ {+ "number": "36",+ "name": "VDD_LV_COR3",+ "type": "power_in",+ "description": "1.2 V PLL module decoupling supply; decoupling capacitor required between this pin and VSS_LV_COR3"+ },+ {+ "number": "37",+ "name": "D[7]",+ "type": "bidirectional",+ "description": "Port D pin 7, programmable as GPIO I/O, DSPI_1 chip select 3, FCU output, or DSPI_0/DSPI_3 serial input"+ },+ {+ "number": "38",+ "name": "G[0]",+ "type": "output",+ "description": "Port G pin 0, programmable as GPIO I/O or FCU output"+ },+ {+ "number": "39",+ "name": "E[1]",+ "type": "input",+ "description": "Port E pin 1, ADC_0 analog input channel AN[4] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "40",+ "name": "E[3]",+ "type": "input",+ "description": "Port E pin 3, ADC_0 analog input channel AN[6] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "41",+ "name": "C[1]",+ "type": "input",+ "description": "Port C pin 1, ADC_0 analog input channel AN[2] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "42",+ "name": "E[4]",+ "type": "input",+ "description": "Port E pin 4, ADC_0 analog input channel AN[7] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "43",+ "name": "B[7]",+ "type": "input",+ "description": "Port B pin 7, ADC_0 analog input channel AN[0] or LIN_0 receive input"+ },+ {+ "number": "44",+ "name": "E[5]",+ "type": "input",+ "description": "Port E pin 5, ADC_0 analog input channel AN[8] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "45",+ "name": "C[2]",+ "type": "input",+ "description": "Port C pin 2, ADC_0 analog input channel AN[3] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "46",+ "name": "E[6]",+ "type": "input",+ "description": "Port E pin 6, ADC_0 analog input channel AN[9] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "47",+ "name": "B[8]",+ "type": "input",+ "description": "Port B pin 8, ADC_0 analog input channel AN[1] or eTimer input"+ },+ {+ "number": "48",+ "name": "E[7]",+ "type": "input",+ "description": "Port E pin 7, ADC_0 analog input channel AN[10] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "49",+ "name": "E[2]",+ "type": "input",+ "description": "Port E pin 2, ADC_0 analog input channel AN[5] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "50",+ "name": "VDD_HV_ADC0",+ "type": "power_in",+ "description": "ADC_0 supply voltage and high reference voltage for 10-bit analog-to-digital converter"+ },+ {+ "number": "51",+ "name": "VSS_HV_ADC0",+ "type": "power_in",+ "description": "ADC_0 ground and low reference voltage for 10-bit analog-to-digital converter"+ },+ {+ "number": "52",+ "name": "B[9]",+ "type": "input",+ "description": "Port B pin 9, shared ADC_0 and ADC_1 analog input channel AN[11] for conversion"+ },+ {+ "number": "53",+ "name": "B[10]",+ "type": "input",+ "description": "Port B pin 10, shared ADC_0 and ADC_1 analog input channel AN[12] for conversion"+ },+ {+ "number": "54",+ "name": "B[11]",+ "type": "input",+ "description": "Port B pin 11, shared ADC_0 and ADC_1 analog input channel AN[13] for conversion"+ },+ {+ "number": "55",+ "name": "B[12]",+ "type": "input",+ "description": "Port B pin 12, shared ADC_0 and ADC_1 analog input channel AN[14] for conversion"+ },+ {+ "number": "56",+ "name": "VDD_HV_ADC1",+ "type": "power_in",+ "description": "ADC_1 supply voltage and high reference voltage for 10-bit analog-to-digital converter"+ },+ {+ "number": "57",+ "name": "VSS_HV_ADC1",+ "type": "power_in",+ "description": "ADC_1 ground and low reference voltage for 10-bit analog-to-digital converter"+ },+ {+ "number": "58",+ "name": "D[15]",+ "type": "input",+ "description": "Port D pin 15, ADC_1 analog input channel AN[4] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "59",+ "name": "E[8]",+ "type": "input",+ "description": "Port E pin 8, ADC_1 analog input channel AN[6] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "60",+ "name": "B[13]",+ "type": "input",+ "description": "Port B pin 13, ADC_1 analog input channel AN[0] or LIN_1 receive input"+ },+ {+ "number": "61",+ "name": "E[9]",+ "type": "input",+ "description": "Port E pin 9, ADC_1 analog input channel AN[7] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "62",+ "name": "B[15]",+ "type": "input",+ "description": "Port B pin 15, ADC_1 analog input channel AN[2] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "63",+ "name": "E[10]",+ "type": "input",+ "description": "Port E pin 10, ADC_1 analog input channel AN[8] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "64",+ "name": "B[14]",+ "type": "input",+ "description": "Port B pin 14, ADC_1 analog input channel AN[1] or eTimer input"+ },+ {+ "number": "65",+ "name": "E[11]",+ "type": "input",+ "description": "Port E pin 11, ADC_1 analog input channel AN[9] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "66",+ "name": "C[0]",+ "type": "input",+ "description": "Port C pin 0, ADC_1 analog input channel AN[3] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "67",+ "name": "E[12]",+ "type": "input",+ "description": "Port E pin 12, ADC_1 analog input channel AN[10] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "68",+ "name": "E[0]",+ "type": "input",+ "description": "Port E pin 0, ADC_1 analog input channel AN[5] for 10-bit analog-to-digital conversion"+ },+ {+ "number": "69",+ "name": "BCTRL",+ "type": "bidirectional",+ "description": "Voltage regulator external NPN ballast transistor base control pin for on-chip regulator"+ },+ {+ "number": "70",+ "name": "VDD_LV_REGCOR",+ "type": "power_in",+ "description": "1.2 V decoupling supply for core logic and regulator feedback; decoupling capacitor required"+ },+ {+ "number": "71",+ "name": "VSS_LV_REGCOR",+ "type": "power_in",+ "description": "1.2 V decoupling ground for core logic and regulator feedback; decoupling capacitor required"+ },+ {+ "number": "72",+ "name": "VDD_HV_REG",+ "type": "power_in",+ "description": "3.3 V or 5.0 V voltage regulator supply voltage input"+ },+ {+ "number": "73",+ "name": "A[0]",+ "type": "bidirectional",+ "description": "Port A pin 0, programmable as GPIO I/O, eTimer input/output, DSPI clock, or external interrupt input"+ },+ {+ "number": "74",+ "name": "A[1]",+ "type": "bidirectional",+ "description": "Port A pin 1, programmable as GPIO I/O, eTimer input/output, DSPI serial output, or external interrupt input"+ },+ {+ "number": "75",+ "name": "G[11]",+ "type": "bidirectional",+ "description": "Port G pin 11, programmable as GPIO I/O or FlexPWM fault input signal"+ },+ {+ "number": "76",+ "name": "D[10]",+ "type": "bidirectional",+ "description": "Port D pin 10, programmable as GPIO I/O, FlexPWM output, or DSPI chip select/clock"+ },+ {+ "number": "77",+ "name": "G[10]",+ "type": "bidirectional",+ "description": "Port G pin 10, programmable as GPIO I/O or FlexPWM fault input signal"+ },+ {+ "number": "78",+ "name": "D[11]",+ "type": "bidirectional",+ "description": "Port D pin 11, programmable as GPIO I/O, FlexPWM output, or DSPI serial input/clock"+ },+ {+ "number": "79",+ "name": "G[9]",+ "type": "bidirectional",+ "description": "Port G pin 9, programmable as GPIO I/O or FlexPWM fault input signal"+ },+ {+ "number": "80",+ "name": "C[11]",+ "type": "bidirectional",+ "description": "Port C pin 11, programmable as GPIO I/O, eTimer input/output, or DSPI chip select/output"+ },+ {+ "number": "81",+ "name": "G[8]",+ "type": "bidirectional",+ "description": "Port G pin 8, programmable as GPIO I/O or FlexPWM fault input signal"+ },+ {+ "number": "82",+ "name": "C[12]",+ "type": "bidirectional",+ "description": "Port C pin 12, programmable as GPIO I/O, eTimer input/output, or DSPI output/input"+ },+ {+ "number": "83",+ "name": "G[7]",+ "type": "output",+ "description": "Port G pin 7, programmable as GPIO I/O or FlexPWM output"+ },+ {+ "number": "84",+ "name": "A[2]",+ "type": "bidirectional",+ "description": "Port A pin 2, programmable as GPIO I/O, eTimer input/output, FlexPWM output, or external interrupt input"+ },+ {+ "number": "85",+ "name": "G[5]",+ "type": "bidirectional",+ "description": "Port G pin 5, programmable as GPIO I/O or FlexPWM channel input"+ },+ {+ "number": "86",+ "name": "TDI",+ "type": "input",+ "description": "Test Data Input for JTAG 1149.1 boundary scan operations"+ },+ {+ "number": "87",+ "name": "TMS",+ "type": "bidirectional",+ "description": "JTAG Test Mode Select and state machine control signal"+ },+ {+ "number": "88",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock input for IEEE 1149.1 Test Access Port"+ },+ {+ "number": "89",+ "name": "TDO",+ "type": "output",+ "description": "Test Data Output from JTAG 1149.1 boundary scan register"+ },+ {+ "number": "90",+ "name": "VSS_HV_IO2",+ "type": "power_in",+ "description": "I/O ground reference for power domain 2"+ },+ {+ "number": "91",+ "name": "VDD_HV_IO2",+ "type": "power_in",+ "description": "3.3 V or 5.0 V input/output supply voltage for I/O power domain 2"+ },+ {+ "number": "92",+ "name": "A[3]",+ "type": "bidirectional",+ "description": "Port A pin 3, programmable as GPIO I/O, eTimer input/output, DSPI chip select, or external interrupt input"+ },+ {+ "number": "93",+ "name": "VDD_LV_COR1",+ "type": "power_in",+ "description": "1.2 V core logic decoupling supply; decoupling capacitor required between this pin and VSS_LV_COR1"+ },+ {+ "number": "94",+ "name": "VSS_LV_COR1",+ "type": "power_in",+ "description": "1.2 V core logic decoupling ground; decoupling capacitor required between this pin and VDD_LV_COR1"+ },+ {+ "number": "95",+ "name": "D[13]",+ "type": "bidirectional",+ "description": "Port D pin 13, programmable as GPIO I/O, FlexPWM output, or DSPI serial output"+ },+ {+ "number": "96",+ "name": "VSS_HV_FL",+ "type": "power_in",+ "description": "Code and data flash module ground reference"+ },+ {+ "number": "97",+ "name": "VDD_HV_FL",+ "type": "power_in",+ "description": "Code and data flash module supply voltage"+ },+ {+ "number": "98",+ "name": "G[6]",+ "type": "output",+ "description": "Port G pin 6, programmable as GPIO I/O or FlexPWM output"+ },+ {+ "number": "99",+ "name": "D[12]",+ "type": "bidirectional",+ "description": "Port D pin 12, programmable as GPIO I/O or FlexPWM channel output"+ },+ {+ "number": "100",+ "name": "G[4]",+ "type": "output",+ "description": "Port G pin 4, programmable as GPIO I/O or FlexPWM output"+ },+ {+ "number": "101",+ "name": "C[13]",+ "type": "bidirectional",+ "description": "Port C pin 13, programmable as GPIO I/O, eTimer input/output, or FlexPWM synchronization input"+ },+ {+ "number": "102",+ "name": "G[2]",+ "type": "bidirectional",+ "description": "Port G pin 2, programmable as GPIO I/O or FlexPWM channel input"+ },+ {+ "number": "103",+ "name": "C[14]",+ "type": "bidirectional",+ "description": "Port C pin 14, programmable as GPIO I/O, eTimer input/output, or CTU trigger input"+ },+ {+ "number": "104",+ "name": "G[3]",+ "type": "output",+ "description": "Port G pin 3, programmable as GPIO I/O or FlexPWM output"+ },+ {+ "number": "105",+ "name": "D[14]",+ "type": "bidirectional",+ "description": "Port D pin 14, programmable as GPIO I/O, FlexPWM output, or DSPI serial output"+ },+ {+ "number": "106",+ "name": "F[12]",+ "type": "bidirectional",+ "description": "Port F pin 12, programmable as GPIO I/O or eTimer input/output"+ },+ {+ "number": "107",+ "name": "VPP_TEST",+ "type": "power_in",+ "description": "Test pin for factory testing purposes only; must be tied to ground VSS in normal operating mode"+ },+ {+ "number": "108",+ "name": "A[4]",+ "type": "bidirectional",+ "description": "Port A pin 4, programmable as GPIO I/O, eTimer input/output, DSPI chip select, or external interrupt input"+ },+ {+ "number": "109",+ "name": "B[0]",+ "type": "bidirectional",+ "description": "Port B pin 0, programmable as GPIO I/O, FlexCAN transmit output, eTimer input/output, or external interrupt input"+ },+ {+ "number": "110",+ "name": "B[1]",+ "type": "bidirectional",+ "description": "Port B pin 1, programmable as GPIO I/O, FlexCAN receive input, or eTimer input/output"+ },+ {+ "number": "111",+ "name": "C[10]",+ "type": "bidirectional",+ "description": "Port C pin 10, programmable as GPIO I/O, DSPI chip select 2, or FlexPWM output"+ },+ {+ "number": "112",+ "name": "F[13]",+ "type": "bidirectional",+ "description": "Port F pin 13, programmable as GPIO I/O or eTimer input/output"+ },+ {+ "number": "113",+ "name": "F[15]",+ "type": "bidirectional",+ "description": "Port F pin 15, programmable as GPIO I/O or LIN_1 receive input"+ },+ {+ "number": "114",+ "name": "B[2]",+ "type": "bidirectional",+ "description": "Port B pin 2, programmable as GPIO I/O or LIN_0 transmit output"+ },+ {+ "number": "115",+ "name": "F[14]",+ "type": "bidirectional",+ "description": "Port F pin 14, programmable as GPIO I/O or LIN_1 transmit output"+ },+ {+ "number": "116",+ "name": "B[3]",+ "type": "bidirectional",+ "description": "Port B pin 3, programmable as GPIO I/O or LIN_0 receive input"+ },+ {+ "number": "117",+ "name": "E[13]",+ "type": "bidirectional",+ "description": "Port E pin 13, programmable as GPIO I/O, DSPI clock input/output, or external interrupt input"+ },+ {+ "number": "118",+ "name": "A[10]",+ "type": "bidirectional",+ "description": "Port A pin 10, programmable as GPIO I/O, DSPI chip select 0, FlexPWM output, or external interrupt input"+ },+ {+ "number": "119",+ "name": "E[14]",+ "type": "bidirectional",+ "description": "Port E pin 14, programmable as GPIO I/O, DSPI serial output, or external interrupt input"+ },+ {+ "number": "120",+ "name": "A[11]",+ "type": "bidirectional",+ "description": "Port A pin 11, programmable as GPIO I/O, DSPI clock output, FlexPWM output, or external interrupt input"+ },+ {+ "number": "121",+ "name": "E[15]",+ "type": "bidirectional",+ "description": "Port E pin 15, programmable as GPIO I/O, DSPI serial input, or external interrupt input"+ },+ {+ "number": "122",+ "name": "A[12]",+ "type": "bidirectional",+ "description": "Port A pin 12, programmable as GPIO I/O, DSPI serial output, FlexPWM output, or external interrupt input"+ },+ {+ "number": "123",+ "name": "C[9]",+ "type": "bidirectional",+ "description": "Port C pin 9, programmable as GPIO I/O, DSPI chip select 3, or FlexPWM channel input/output"+ },+ {+ "number": "124",+ "name": "C[15]",+ "type": "bidirectional",+ "description": "Port C pin 15, programmable as GPIO I/O, FlexRay enable output, eTimer input/output, or FlexPWM output/sync input"+ },+ {+ "number": "125",+ "name": "D[0]",+ "type": "bidirectional",+ "description": "Port D pin 0, programmable as GPIO I/O, FlexRay transmit output, eTimer input/output, or FlexPWM output"+ },+ {+ "number": "126",+ "name": "VDD_HV_IO3",+ "type": "power_in",+ "description": "3.3 V or 5.0 V input/output supply voltage for I/O power domain 3"+ },+ {+ "number": "127",+ "name": "VSS_HV_IO3",+ "type": "power_in",+ "description": "I/O ground reference for power domain 3"+ },+ {+ "number": "128",+ "name": "D[3]",+ "type": "bidirectional",+ "description": "Port D pin 3, programmable as GPIO I/O, FlexRay transmit output, eTimer input/output, or FlexPWM output"+ },+ {+ "number": "129",+ "name": "D[4]",+ "type": "bidirectional",+ "description": "Port D pin 4, programmable as GPIO I/O, FlexRay enable output, eTimer input/output, or FlexPWM output"+ },+ {+ "number": "130",+ "name": "C[8]",+ "type": "bidirectional",+ "description": "Port C pin 8, programmable as GPIO I/O, DSPI chip select 1, or FlexPWM output"+ },+ {+ "number": "131",+ "name": "VDD_LV_COR2",+ "type": "power_in",+ "description": "1.2 V core logic decoupling supply; decoupling capacitor required between this pin and VSS_LV_COR2"+ },+ {+ "number": "132",+ "name": "VSS_LV_COR2",+ "type": "power_in",+ "description": "1.2 V core logic decoupling ground; decoupling capacitor required between this pin and VDD_LV_COR2"+ },+ {+ "number": "133",+ "name": "F[0]",+ "type": "bidirectional",+ "description": "Port F pin 0, programmable as GPIO I/O, FlexRay debug output, or DSPI chip select 3"+ },+ {+ "number": "134",+ "name": "A[9]",+ "type": "bidirectional",+ "description": "Port A pin 9, programmable as GPIO I/O, DSPI chip select 1, FlexPWM output, or fault input"+ },+ {+ "number": "135",+ "name": "F[1]",+ "type": "bidirectional",+ "description": "Port F pin 1, programmable as GPIO I/O, FlexRay debug output, or DSPI chip select 2"+ },+ {+ "number": "136",+ "name": "A[13]",+ "type": "bidirectional",+ "description": "Port A pin 13, programmable as GPIO I/O, DSPI serial input, FlexPWM output, or external interrupt input"+ },+ {+ "number": "137",+ "name": "F[2]",+ "type": "bidirectional",+ "description": "Port F pin 2, programmable as GPIO I/O, FlexRay debug output, or DSPI chip select 1"+ },+ {+ "number": "138",+ "name": "B[6]",+ "type": "bidirectional",+ "description": "Port B pin 6, programmable as GPIO I/O, clock output, DSPI chip select 2, or external interrupt input"+ },+ {+ "number": "139",+ "name": "F[3]",+ "type": "bidirectional",+ "description": "Port F pin 3, programmable as GPIO I/O, FlexRay chip select output, or DSPI serial input"+ },+ {+ "number": "140",+ "name": "D[2]",+ "type": "bidirectional",+ "description": "Port D pin 2, programmable as GPIO I/O, eTimer input/output, FlexPWM channel input, or FlexRay receive input"+ },+ {+ "number": "141",+ "name": "G[1]",+ "type": "output",+ "description": "Port G pin 1, programmable as GPIO I/O or FCU output"+ },+ {+ "number": "142",+ "name": "C[6]",+ "type": "bidirectional",+ "description": "Port C pin 6, programmable as GPIO I/O, DSPI serial output, FlexPWM output, or external interrupt input"+ },+ {+ "number": "143",+ "name": "A[14]",+ "type": "bidirectional",+ "description": "Port A pin 14, programmable as GPIO I/O, Safety Port transmit output, eTimer input/output, or external interrupt input"+ },+ {+ "number": "144",+ "name": "A[15]",+ "type": "bidirectional",+ "description": "Port A pin 15, programmable as GPIO I/O, Safety Port receive input, eTimer input/output, or external interrupt input"+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Datasheet provides functional descriptions and pin muxing options, but does not explicitly state ele"+ ],+ "pages_sent": 36,+ "cost_usd": 0.619,+ "at": "2026-10-07T07:51:30"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588942362793398272",+ "pages": 112,+ "sha256": "d835583856bd2db4",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 144,+ "described": 144,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "spc560p50l5cefar.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 22,+ 22,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b4d698da8bb7697b754adb5655c932342462d9b9341cdaa081b3604dbdf7559b",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "spc560p50l5cefar-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 22,+ 22,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "0bbd6ed517bd0398cb34308a8a436c3e8456663b075081de921fb242a9530268",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}