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SPC560D40L1C4E0X

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SPC560D40L1C4E0X

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

SPC560D40L1C4E0X from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB[3] bidirectional GPIO PB[3] (GPIO[19]) also multiplexed with LIN0RX and the WKPU[11] wakeup input; slow pad, tristate during reset.
2 PC[9] bidirectional GPIO PC[9] also multiplexed with E0UC[7], LIN2RX and the WKPU[13] wakeup input; slow pad, tristate during reset.
3 PA[2] bidirectional GPIO PA[2] also multiplexed with E0UC[2], MA[2] ADC output and the WKPU[3] wakeup input; slow pad, tristate during reset.
4 PA[1] bidirectional GPIO PA[1] also multiplexed with E0UC[1], NMI (which has priority over the alternate function when selected) and the WKPU[2] wakeup input; slow pad, tristate during reset.
5 PA[0] bidirectional GPIO PA[0] also multiplexed with E0UC[0], CLKOUT, E0UC[13] and the WKPU[19] wakeup input; medium pad, tristate during reset.
6 VSS_HV power_in Digital ground.
7 VDD_HV power_in Digital supply voltage; the high voltage supply is 5.0 V or 3.3 V as selected by NVUSRO[PAD3V5V].
8 VSS_HV power_in Digital ground.
9 RESET bidirectional Bidirectional reset with Schmitt-Trigger characteristics and noise filter; the pad is driven low during reset and is pulled up only after PHASE2 reset completion.
10 VSS_LV power_in 1.2 V decoupling pin; a decoupling capacitor must be connected between this pin and the nearest VDD_LV pin.
11 VDD_LV power_in 1.2 V decoupling pin; a decoupling capacitor must be connected between this pin and the nearest VSS_LV pin.
12 VDD_BV power_in Internal regulator supply voltage.
13 PC[10] bidirectional GPIO PC[10] also multiplexed with the MA[1] ADC output; medium pad, tristate during reset.
14 PB[0] bidirectional GPIO PB[0] also multiplexed with CAN0TX (FlexCAN_0) and LIN2TX outputs; medium pad, tristate during reset.
15 PB[1] bidirectional GPIO PB[1] also multiplexed with LIN0RX, CAN0RX and the WKPU[4] wakeup input; slow pad, tristate during reset.
16 PC[6] bidirectional GPIO PC[6] also multiplexed with the LIN1TX output; slow pad, tristate during reset.
17 PC[7] bidirectional GPIO PC[7] also multiplexed with LIN1RX and the WKPU[12] wakeup input; slow pad, tristate during reset.
18 PA[15] bidirectional GPIO PA[15] also multiplexed with CS0_0, SCK_0, E0UC[1] and the WKPU[10] wakeup input; medium pad, tristate during reset.
19 PA[14] bidirectional GPIO PA[14] also multiplexed with SCK_0, CS0_0, E0UC[0] and EIRQ[4]; medium pad, tristate during reset.
20 PA[4] bidirectional GPIO PA[4] also multiplexed with E0UC[4], CS0_1 and the WKPU[9] wakeup input; slow pad, tristate during reset.
21 PA[13] bidirectional GPIO PA[13] also multiplexed with SOUT_0, CS3_1 and DSPI_1 functions; medium pad, tristate during reset.
22 PA[12] bidirectional GPIO PA[12] also multiplexed with the SIN_0 (DSPI_0) input and EIRQ[17]; slow pad, tristate during reset.
23 VDD_LV power_in 1.2 V decoupling pin; a decoupling capacitor must be connected between this pin and the nearest VSS_LV pin.
24 VSS_LV power_in 1.2 V decoupling pin; a decoupling capacitor must be connected between this pin and the nearest VDD_LV pin.
25 XTAL input Analog input of the oscillator amplifier circuit; it needs to be grounded if the oscillator is used in bypass mode.
26 VSS_HV power_in Digital ground.
27 EXTAL bidirectional Analog output of the oscillator amplifier when the oscillator is not in bypass mode; analog input for the clock generator when the oscillator is in bypass mode.
28 VDD_HV power_in Digital supply voltage; the high voltage supply is 5.0 V or 3.3 V as selected by NVUSRO[PAD3V5V].
29 PB[9] input Input-only analog pad ADC1_S[5], also multiplexed with the WKPU[26] wakeup input; tristate during reset.
30 PB[8] input Input-only analog pad ADC1_S[4], also multiplexed with the WKPU[25] wakeup input; tristate during reset.
31 PB[10] bidirectional GPIO PB[10] (I/O pad with analog feature) also multiplexed with ADC1_S[6] and the WKPU[8] wakeup input; tristate during reset.
32 PB[4] input Input-only analog pad ADC1_P[0]; tristate during reset.
33 VSS_HV power_in Digital ground per Table 4; Figure 3 labels the ADC ground as VSS_HV_ADC.
34 VDD_HV power_in Digital supply voltage per Table 4; Figure 3 labels the ADC supply as VDD_HV_ADC; the high voltage supply is 5.0 V or 3.3 V as selected by NVUSRO[PAD3V5V].
35 PB[5] input Input-only analog pad ADC1_P[1]; tristate during reset.
36 PB[6] input Input-only analog pad ADC1_P[2]; tristate during reset.
37 PB[7] input Input-only analog pad ADC1_P[3]; the precise ADC pad has no output buffer and is left tristate during reset.
38 PB[11] bidirectional GPIO PB[11] (I/O pad with analog feature) also multiplexed with E0UC[3], CS0_0 and ADC1_S[12]; tristate during reset.
39 PB[12] bidirectional GPIO PB[12] (I/O pad with analog feature) also multiplexed with E0UC[4], CS1_0 and ADC1_X[0]; tristate during reset.
40 PB[13] bidirectional GPIO PB[13] (I/O pad with analog feature) also multiplexed with E0UC[5], CS2_0 and ADC1_X[1]; tristate during reset.
41 PB[14] bidirectional GPIO PB[14] (I/O pad with analog feature) also multiplexed with E0UC[6], CS3_0 and ADC1_X[2]; tristate during reset.
42 PB[15] bidirectional GPIO PB[15] (I/O pad with analog feature) also multiplexed with E0UC[7], CS4_0 and ADC1_X[3]; tristate during reset.
43 PA[3] bidirectional GPIO PA[3] also multiplexed with E0UC[3], CS4_0, EIRQ[0] and the ADC1_S[0] analog input; slow pad, tristate during reset.
44 PA[7] bidirectional GPIO PA[7] also multiplexed with E0UC[7], EIRQ[2] and the ADC1_S[1] analog input; slow pad, tristate during reset.
45 PA[8] input Pad with weak pull-up after reset, also multiplexed with E0UC[8], E0UC[14], EIRQ[3] and the ABS[0] boot-assist input (ABS function is only available while the device is booting).
46 PA[9] input Pad with pull-down after power-up; the FAB input without an external strong pull-up makes the device start fetching from flash, also multiplexed with E0UC[9] and CS2_1.
47 PA[10] bidirectional GPIO PA[10] also multiplexed with E0UC[10], the LIN2TX output and the ADC1_S[2] analog input; slow pad, tristate during reset.
48 PA[11] bidirectional GPIO PA[11] also multiplexed with E0UC[11], EIRQ[16], the LIN2RX input and the ADC1_S[3] analog input; slow pad, tristate during reset.
49 PC[3] bidirectional GPIO PC[3] also multiplexed with CS0_1, the MA[0] ADC output and EIRQ[6]; slow pad, tristate during reset.
50 PC[2] bidirectional GPIO PC[2] also multiplexed with SCK_1 and EIRQ[5]; medium pad, tristate during reset.
51 PA[5] bidirectional GPIO PA[5] also multiplexed with E0UC[5]; medium pad, tristate during reset.
52 PA[6] bidirectional GPIO PA[6] also multiplexed with E0UC[6], CS1_1 and EIRQ[1]; slow pad, tristate during reset.
53 PH[10] input JTAG TMS input with weak pull-up; if configured as GPIO the device is no longer compliant with IEEE 1149.1-2001.
54 PC[1] tri_state JTAG TDO output, tristate during reset (fast pad); if configured as GPIO the device is no longer compliant with IEEE 1149.1-2001.
55 VSS_HV power_in Digital ground.
56 VDD_HV power_in Digital supply voltage; the high voltage supply is 5.0 V or 3.3 V as selected by NVUSRO[PAD3V5V].
57 VDD_LV power_in 1.2 V decoupling pin; a decoupling capacitor must be connected between this pin and the nearest VSS_LV pin.
58 VSS_LV power_in 1.2 V decoupling pin; a decoupling capacitor must be connected between this pin and the nearest VDD_LV pin.
59 PC[0] input JTAG TDI input with weak pull-up; if configured as GPIO the device is no longer compliant with IEEE 1149.1-2001.
60 PH[9] input JTAG TCK input with weak pull-up; if configured as GPIO the device is no longer compliant with IEEE 1149.1-2001.
61 PC[5] bidirectional GPIO PC[5] also multiplexed with SOUT_1 and EIRQ[7]; medium pad, tristate during reset.
62 PC[4] bidirectional GPIO PC[4] also multiplexed with SIN_1 and EIRQ[18]; medium pad, tristate during reset.
63 PC[8] bidirectional GPIO PC[8] also multiplexed with the LIN2TX output and E0UC[3]; slow pad, tristate during reset.
64 PB[2] bidirectional GPIO PB[2] also multiplexed with the LIN0TX output; medium pad, tristate during reset.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: SPC560D40L1C4E0X
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: spc560d40l1c4e0x-etched.step / spc560d40l1c4e0x-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); spc560d40l1c4e0x.step / spc560d40l1c4e0x.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (82 pp, sha256 62e387a7eee269ae, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF