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SPC560C50L3C6E0X

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersspc560c50l3c6e0xfactory-2.0.0extractor-text
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Contents

README

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SPC560C50L3C6E0X

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

SPC560C50L3C6E0X from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB[3] bidirectional Slow GPIO[19] also used as I2C_0 SCL, LIN0RX and WKPU[11] wakeup input; tristate at reset.
2 PC[9] bidirectional Slow GPIO[41] also used as LIN2RX and WKPU[13] wakeup input; tristate at reset.
3 PC[14] bidirectional Slow GPIO[46] also used as eMIOS_0 E0UC[14], DSPI_2 SCK_2 and EIRQ[8]; tristate at reset.
4 PC[15] bidirectional Medium GPIO[47] also used as eMIOS_0 E0UC[15] and DSPI_2 CS0_2; tristate at reset.
5 PA[2] bidirectional Slow GPIO[2] also used as eMIOS_0 E0UC[2] and WKPU[3] wakeup input; tristate at reset.
6 PE[0] bidirectional Slow GPIO[64] also used as eMIOS_0 E0UC[16], FlexCAN_5 CAN5RX and WKPU[6] wakeup input; tristate at reset.
7 PA[1] bidirectional Slow GPIO[1] also used as eMIOS_0 E0UC[1], NMI and WKPU[2] wakeup input; tristate at reset.
8 PE[1] bidirectional Medium GPIO[65] also used as eMIOS_0 E0UC[17] and FlexCAN_5 CAN5TX; tristate at reset.
9 PE[8] bidirectional Medium GPIO[72] also used as FlexCAN_2 CAN2TX, eMIOS_0 E0UC[22] and FlexCAN_3 CAN3TX; tristate at reset.
10 PE[9] bidirectional Slow GPIO[73] also used as eMIOS_0 E0UC[23], FlexCAN_2 CAN2RX, FlexCAN_3 CAN3RX and WKPU[7]; tristate at reset.
11 PE[10] bidirectional Slow GPIO[74] also used as LINFlex_3 LIN3TX, DSPI_1 CS3_1 and EIRQ[10]; tristate at reset.
12 PA[0] bidirectional Medium GPIO[0] also used as eMIOS_0 E0UC[0], CLKOUT and WKPU[19] wakeup input; tristate at reset.
13 PE[11] bidirectional Slow GPIO[75] also used as DSPI_1 CS4_1, LINFlex_3 LIN3RX and WKPU[14]; tristate at reset.
14 VSS_HV power_in Digital ground of the high-voltage domain (0 V reference).
15 VDD_HV power_in Digital I/O and regulator supply: 3.0-3.6 V (3.3 V operation) or 4.5-5.5 V (5.0 V operation), with 100 nF per VDD/VSS pair (Tables 13 and 14).
16 VSS_HV power_in Digital ground of the high-voltage domain (0 V reference).
17 RESET bidirectional Bidirectional reset with Schmitt-trigger input and noise filter; driven low during power-up and weak pull-up only after PHASE2 reset completion.
18 VSS_LV power_in 1.2 V low-voltage decoupling pin; a 330 nF capacitor is required between each VDD_LV/VSS_LV pair.
19 VDD_LV power_in 1.2 V low-voltage (core) decoupling pin; a 330 nF capacitor is required between each VDD_LV/VSS_LV pair.
20 VDD_BV power_in Internal regulator (ballast) supply, 3.0-3.6 V or 4.5-5.5 V relative to VSS, with 400 nF (3.3 V) or 100 nF (5.0 V) to the nearest VSS_LV.
21 PC[11] bidirectional Slow GPIO[43] also used as FlexCAN_1 CAN1RX, FlexCAN_4 CAN4RX and WKPU[5] wakeup input; tristate at reset.
22 PC[10] bidirectional Medium GPIO[42] also used as FlexCAN_1 CAN1TX, FlexCAN_4 CAN4TX and ADC MA[1]; tristate at reset.
23 PB[0] bidirectional Medium GPIO[16] also used as FlexCAN_0 CAN0TX; tristate at reset.
24 PB[1] bidirectional Slow GPIO[17] also used as FlexCAN_0 CAN0RX and WKPU[4] wakeup input; tristate at reset.
25 PC[6] bidirectional Slow GPIO[38] also used as LINFlex_1 LIN1TX; tristate at reset.
26 PC[7] bidirectional Slow GPIO[39] also used as LINFlex_1 LIN1RX and WKPU[12] wakeup input; tristate at reset.
27 PA[15] bidirectional Medium GPIO[15] also used as DSPI_0 CS0_0 and SCK_0 and WKPU[10] wakeup input; tristate at reset.
28 PA[14] bidirectional Medium GPIO[14] also used as DSPI_0 SCK_0, CS0_0 and EIRQ[4]; tristate at reset.
29 PA[4] bidirectional Slow GPIO[4] also used as eMIOS_0 E0UC[4] and WKPU[9] wakeup input; tristate at reset.
30 PA[13] bidirectional Medium GPIO[13] also used as DSPI_0 SOUT_0; tristate at reset.
31 PA[12] bidirectional Slow GPIO[12] also used as DSPI_0 SIN_0; tristate at reset.
32 VDD_LV power_in 1.2 V low-voltage (core) decoupling pin; a 330 nF capacitor is required between each VDD_LV/VSS_LV pair.
33 VSS_LV power_in 1.2 V low-voltage decoupling ground; the decoupling capacitor must sit between this pin and the nearest VDD_LV pin.
34 XTAL input Analog input of the fast crystal oscillator amplifier; must be grounded when the oscillator is used in bypass mode.
35 VSS_HV power_in Digital ground of the high-voltage domain (0 V reference).
36 EXTAL bidirectional Analog output of the oscillator amplifier when not in bypass mode; analog clock input when the oscillator is in bypass mode (4 to 16 MHz fast crystal).
37 VDD_HV power_in Digital I/O and regulator supply: 3.0-3.6 V (3.3 V operation) or 4.5-5.5 V (5.0 V operation), with 100 nF per VDD/VSS pair (Tables 13 and 14).
38 PB[9] passive Input-only analog pad used as OSC32K_EXTAL (32 kHz crystal) and ANS[1]; PCR.IBE must be 0 when used by the oscillator.
39 PB[8] passive Input-only analog pad used as OSC32K_XTAL (32 kHz crystal) and ANS[0]; PCR.IBE must be 0 when used by the oscillator.
40 PB[10] bidirectional Analog-capable (J) GPIO[26] also used as ADC ANS[2] and WKPU[8] wakeup input; tristate at reset.
41 PD[0] input Input-only precise ADC pad GPI[4] / ANS channel with no output buffer; tristate at reset.
42 PD[1] input Input-only precise ADC pad GPI[5] with no output buffer; tristate at reset.
43 PD[2] input Input-only precise ADC pad GPI[6] with no output buffer; tristate at reset.
44 PD[3] input Input-only precise ADC pad GPI[7] with no output buffer; tristate at reset.
45 PD[4] input Input-only precise ADC pad GPI[8] with no output buffer; tristate at reset.
46 PD[5] input Input-only precise ADC pad GPI[9] with no output buffer; tristate at reset.
47 PD[6] input Input-only precise ADC pad GPI[10] with no output buffer; tristate at reset.
48 PD[7] input Input-only precise ADC pad GPI[11] with no output buffer; tristate at reset.
49 PD[8] input Input-only precise ADC pad GPI[12] with no output buffer; tristate at reset.
50 PB[4] input Input-only precise ADC pad GPI[0] with no output buffer; tristate at reset.
51 VSS_HV_ADC power_in Reference and analog ground for the ADC, to be tied to VSS within ±0.1 V.
52 VDD_HV_ADC power_in ADC reference and analog supply, 3.0-3.6 V or 4.5-5.5 V; 100 nF (3.3 V) or 1 µF + 47 nF (5.0 V) to VSS_HV_ADC.
53 PB[5] input Input-only precise ADC pad GPI[1] with no output buffer; tristate at reset.
54 PB[6] input Input-only precise ADC pad GPI[2] with no output buffer; tristate at reset.
55 PB[7] input Input-only precise ADC pad GPI[3] with no output buffer; tristate at reset.
56 PD[9] input Input-only precise ADC pad GPI[13] with no output buffer; tristate at reset.
57 PD[10] input Input-only precise ADC pad GPI[14] with no output buffer; tristate at reset.
58 PD[11] input Input-only precise ADC pad GPI[15] with no output buffer; tristate at reset.
59 PB[11] bidirectional Analog-capable (J) GPIO[27] also used as eMIOS_0 E0UC[3], DSPI_0 CS0_0 and ADC ANS[3]; tristate at reset.
60 PD[12] bidirectional Analog-capable (J) GPIO[60] also used as DSPI_0 CS5_0, eMIOS_0 E0UC[24] and ADC ANS[4]; tristate at reset.
61 PB[12] bidirectional Analog-capable (J) GPIO[28] also used as eMIOS_0 E0UC[4], DSPI_0 CS1_0 and ADC ANX[0]; tristate at reset.
62 PD[13] bidirectional Analog-capable (J) GPIO[61] also used as DSPI_1 CS0_1, eMIOS_0 E0UC[25] and ADC ANS[5]; tristate at reset.
63 PB[13] bidirectional Analog-capable (J) GPIO[29] also used as eMIOS_0 E0UC[5], DSPI_0 CS2_0 and ADC ANX[1]; tristate at reset.
64 PD[14] bidirectional Analog-capable (J) GPIO[62] also used as DSPI_1 CS1_1, eMIOS_0 E0UC[26] and ADC ANS[6]; tristate at reset.
65 PB[14] bidirectional Analog-capable (J) GPIO[30] also used as eMIOS_0 E0UC[6], DSPI_0 CS3_0 and ADC ANX[2]; tristate at reset.
66 PD[15] bidirectional Analog-capable (J) GPIO[63] also used as DSPI_1 CS2_1, eMIOS_0 E0UC[27] and ADC ANS[7]; tristate at reset.
67 PB[15] bidirectional Analog-capable (J) GPIO[31] also used as eMIOS_0 E0UC[7], DSPI_0 CS4_0 and ADC ANX[3]; tristate at reset.
68 PA[3] bidirectional Slow GPIO[3] also used as eMIOS_0 E0UC[3] and EIRQ[0]; tristate at reset.
69 VSS_HV power_in Digital ground of the high-voltage domain (0 V reference).
70 VDD_HV power_in Digital I/O and regulator supply: 3.0-3.6 V (3.3 V operation) or 4.5-5.5 V (5.0 V operation), with 100 nF per VDD/VSS pair (Tables 13 and 14).
71 PA[7] bidirectional Slow GPIO[7] also used as eMIOS_0 E0UC[7], LINFlex_3 LIN3TX and EIRQ[2]; tristate at reset.
72 PA[8] bidirectional Slow GPIO[8] also used as eMIOS_0 E0UC[8], EIRQ[3], BAM ABS[0] and LINFlex_3 LIN3RX; weak pull-up at reset.
73 PA[9] bidirectional Slow GPIO[9] also used as eMIOS_0 E0UC[9] and BAM FAB; pull-down at reset, so without a strong external pull-up the device starts fetching from flash.
74 PA[10] bidirectional Slow GPIO[10] also used as eMIOS_0 E0UC[10] and I2C_0 SDA; tristate at reset.
75 PA[11] bidirectional Slow GPIO[11] also used as eMIOS_0 E0UC[11] and I2C_0 SCL; tristate at reset.
76 PE[12] bidirectional Slow GPIO[76] also used as DSPI_2 SIN_2 and EIRQ[11]; E1UC[19] is not available in the 100-pin LQFP package; tristate at reset.
77 PC[3] bidirectional Slow GPIO[35] also used as DSPI_1 CS0_1, ADC MA[0], FlexCAN_1 CAN1RX, FlexCAN_4 CAN4RX and EIRQ[6]; tristate at reset.
78 PC[2] bidirectional Medium GPIO[34] also used as DSPI_1 SCK_1, FlexCAN_4 CAN4TX and EIRQ[5]; tristate at reset.
79 PA[5] bidirectional Medium GPIO[5] also used as eMIOS_0 E0UC[5]; tristate at reset.
80 PA[6] bidirectional Slow GPIO[6] also used as eMIOS_0 E0UC[6] and EIRQ[1]; tristate at reset.
81 PH[10] bidirectional Slow GPIO[122] also serving as JTAG TMS input; weak pull-up at reset, and if configured as GPIO the device no longer complies with IEEE 1149.1.
82 PC[1] bidirectional Medium GPIO[33] also serving as JTAG TDO; tristate at reset, and an external 47-100 kΩ pull-up to VDD_HV is required to avoid extra standby current.
83 VSS_HV power_in Digital ground of the high-voltage domain (0 V reference).
84 VDD_HV power_in Digital I/O and regulator supply: 3.0-3.6 V (3.3 V operation) or 4.5-5.5 V (5.0 V operation), with 100 nF per VDD/VSS pair (Tables 13 and 14).
85 VDD_LV power_in 1.2 V low-voltage (core) decoupling pin; a 330 nF capacitor is required between each VDD_LV/VSS_LV pair.
86 VSS_LV power_in 1.2 V low-voltage decoupling ground; the decoupling capacitor must sit between this pin and the nearest VDD_LV pin.
87 PC[0] bidirectional Medium GPIO[32] also serving as JTAG TDI input; weak pull-up at reset, and if configured as GPIO the device no longer complies with IEEE 1149.1.
88 PH[9] bidirectional Slow GPIO[121] also serving as JTAG TCK input; weak pull-up at reset, and if configured as GPIO the device no longer complies with IEEE 1149.1.
89 PE[2] bidirectional Medium GPIO[66] also used as eMIOS_0 E0UC[18] and DSPI_1 SIN_1; tristate at reset.
90 PE[3] bidirectional Medium GPIO[67] also used as eMIOS_0 E0UC[19] and DSPI_1 SOUT_1; tristate at reset.
91 PC[5] bidirectional Medium GPIO[37] also used as DSPI_1 SOUT_1, FlexCAN_3 CAN3TX and EIRQ[7]; tristate at reset.
92 PC[4] bidirectional Medium GPIO[36] also used as DSPI_1 SIN_1 and FlexCAN_3 CAN3RX; tristate at reset.
93 PE[4] bidirectional Medium GPIO[68] also used as eMIOS_0 E0UC[20], DSPI_1 SCK_1 and EIRQ[9]; tristate at reset.
94 PE[5] bidirectional Medium GPIO[69] also used as eMIOS_0 E0UC[21], DSPI_1 CS0_1 and ADC MA[2]; tristate at reset.
95 PE[6] bidirectional Medium GPIO[70] also used as eMIOS_0 E0UC[22], DSPI_0 CS3_0 and ADC MA[1]; tristate at reset.
96 PE[7] bidirectional Medium GPIO[71] also used as eMIOS_0 E0UC[23], DSPI_0 CS2_0 and ADC MA[0]; tristate at reset.
97 PC[12] bidirectional Medium GPIO[44] also used as eMIOS_0 E0UC[12] and DSPI_2 SIN_2; tristate at reset.
98 PC[13] bidirectional Slow GPIO[45] also used as eMIOS_0 E0UC[13] and DSPI_2 SOUT_2; tristate at reset.
99 PC[8] bidirectional Slow GPIO[40] also used as LINFlex_2 LIN2TX; tristate at reset.
100 PB[2] bidirectional Medium GPIO[18] also used as LINFlex_0 LIN0TX and I2C_0 SDA; tristate at reset.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: SPC560C50L3C6E0X
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: spc560c50l3c6e0x-etched.step / spc560c50l3c6e0x-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); spc560c50l3c6e0x.step / spc560c50l3c6e0x.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (116 pp, sha256 17b37543a9b5ee31, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF