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SPC560B64L7C6E0X

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-176(24x24). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SPC560B64L7C6E0X

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-176(24x24)

SPC560B64L7C6E0X from STMicroelectronics, in a LQFP-176(24x24). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB[3] bidirectional GPIO PB[3] (S pad, tristate at reset) also carries E0UC[31], SCL (I2C_0), WKPU[11] and LIN0RX.
2 PC[9] bidirectional GPIO PC[9] (S pad, tristate at reset) also carries E0UC[7], DEBUG[7], WKPU[13] and LIN2RX.
3 PC[14] bidirectional GPIO PC[14] (S pad, tristate at reset) also carries E0UC[14], SCK_2 (DSPI_2) and EIRQ[8].
4 PC[15] bidirectional GPIO PC[15] (M pad, tristate at reset) also carries E0UC[15], CS0_2 (DSPI_2) and EIRQ[20].
5 PJ[4] bidirectional GPIO PJ[4] (M pad, tristate at reset) also carries SCK_5 (DSPI_5) and E1UC[18].
6 VDD_HV power_in Digital supply voltage (high-voltage domain).
7 VSS_HV power_in Digital ground.
8 PH[15] bidirectional GPIO PH[15] (M pad, tristate at reset) also carries SOUT_5 (DSPI_5) and E1UC[17].
9 PH[13] bidirectional GPIO PH[13] (M pad, tristate at reset) also carries SOUT_4, CS0_3 (DSPI_3/DSPI_4) and E1UC[26].
10 PH[14] bidirectional GPIO PH[14] (M pad, tristate at reset) also carries SCK_4, CS1_3 (DSPI_3/DSPI_4) and E1UC[27].
11 PI[6] bidirectional GPIO PI[6] (S pad, tristate at reset) also carries E1UC[30] and CS0_4 (DSPI_4).
12 PI[7] bidirectional GPIO PI[7] (S pad, tristate at reset) also carries E1UC[31] and CS1_4 (DSPI_4).
13 PG[5] bidirectional GPIO PG[5] (S pad, tristate at reset) also carries E1UC[14], SIN_3 (DSPI_3) and WKPU[18].
14 PG[4] bidirectional GPIO PG[4] (M pad, tristate at reset) also carries E1UC[13] and SCK_3 (DSPI_3).
15 PG[3] bidirectional GPIO PG[3] (S pad, tristate at reset) also carries E1UC[12], CS0_3 (DSPI_3) and WKPU[17].
16 PG[2] bidirectional GPIO PG[2] (M pad, tristate at reset) also carries E1UC[11] and SOUT_3 (DSPI_3).
17 PA[2] bidirectional GPIO PA[2] (S pad, tristate at reset) also carries E0UC[2], MA[2] (ADC_0) and WKPU[3].
18 PE[0] bidirectional GPIO PE[0] (S pad, tristate at reset) also carries E0UC[16], CAN5RX (FlexCAN_5) and WKPU[6].
19 PA[1] bidirectional GPIO PA[1] (S pad, tristate at reset) also carries E0UC[1], NMI (higher priority than the alternate function) and WKPU[2].
20 PE[1] bidirectional GPIO PE[1] (M pad, tristate at reset) also carries E0UC[17] and CAN5TX.
21 PE[8] bidirectional GPIO PE[8] (M pad, tristate at reset) also carries CAN2TX, E0UC[22] and CAN3TX.
22 PE[9] bidirectional GPIO PE[9] (S pad, tristate at reset) also carries E0UC[23], CAN2RX, CAN3RX and WKPU[7].
23 PE[10] bidirectional GPIO PE[10] (S pad, tristate at reset) also carries LIN3TX, CS3_1 (DSPI_1), E1UC[30] and EIRQ[10].
24 PA[0] bidirectional GPIO PA[0] (M pad, tristate at reset) also carries E0UC[0], CLKOUT, E0UC[13] and WKPU[19].
25 PE[11] bidirectional GPIO PE[11] (S pad, tristate at reset) also carries E0UC[24], CS4_1 (DSPI_1), LIN3RX and WKPU[14].
26 VSS_HV power_in Digital ground.
27 VDD_HV power_in Digital supply voltage (high-voltage domain).
28 VSS_HV power_in Digital ground.
29 RESET bidirectional Bidirectional reset pad (M pad) with Schmitt-trigger characteristics and noise filter, input weak pull-up after RGM PHASE2 and 40 FIRC cycles.
30 VSS_LV power_in 1.2 V regulator decoupling pin; a decoupling capacitor must be connected between this pin and the nearest VDD_LV pin.
31 VDD_LV power_in 1.2 V regulator decoupling pin; a decoupling capacitor must be connected between this pin and the nearest VSS_LV pin.
32 VDD_BV power_in Internal regulator supply voltage.
33 PG[9] bidirectional GPIO PG[9] (S pad, tristate at reset) also carries E1UC[18], SCK_2 (DSPI_2), LIN7RX and WKPU[21].
34 PG[8] bidirectional GPIO PG[8] (S pad, tristate at reset) also carries E1UC[17], LIN7TX, CS0_2 (DSPI_2) and EIRQ[15].
35 PC[11] bidirectional GPIO PC[11] (S pad, tristate at reset) also carries MA[2] (ADC_0), CAN1RX, CAN4RX and WKPU[5].
36 PC[10] bidirectional GPIO PC[10] (M pad, tristate at reset) also carries CAN1TX, CAN4TX and MA[1] (ADC_0).
37 PG[7] bidirectional GPIO PG[7] (S pad, tristate at reset) also carries E1UC[16], E1UC[30], LIN6RX and WKPU[20].
38 PG[6] bidirectional GPIO PG[6] (M pad, tristate at reset) also carries E1UC[15] and LIN6TX.
39 PB[0] bidirectional GPIO PB[0] (M pad, tristate at reset) also carries CAN0TX, E0UC[30] and LIN0TX.
40 PB[1] bidirectional GPIO PB[1] (S pad, tristate at reset) also carries E0UC[31], CAN0RX, LIN0RX and WKPU[4].
41 PF[9] bidirectional GPIO PF[9] (S pad, tristate at reset) also carries E1UC[1], CS5_0 (DSPI_0), CAN2RX, CAN3RX and WKPU[22].
42 PF[8] bidirectional GPIO PF[8] (M pad, tristate at reset) also carries CAN3TX, CS4_0 (DSPI_0) and CAN2TX.
43 PF[12] bidirectional GPIO PF[12] (M pad, tristate at reset) also carries E1UC[25] and LIN5TX.
44 PC[6] bidirectional GPIO PC[6] (S pad, tristate at reset) also carries LIN1TX, E1UC[28] and DEBUG[4].
45 PC[7] bidirectional GPIO PC[7] (S pad, tristate at reset) also carries E1UC[29], LIN1RX, DEBUG[5] and WKPU[12].
46 PF[10] bidirectional GPIO PF[10] (M pad, tristate at reset) also carries CS1_0 (DSPI_0), LIN4TX and E1UC[2].
47 PF[11] bidirectional GPIO PF[11] (S pad, tristate at reset) also carries CS2_0 (DSPI_0), E1UC[3], LIN4RX and WKPU[15].
48 PA[15] bidirectional GPIO PA[15] (M pad, tristate at reset) also carries CS0_0 and SCK_0 (DSPI_0), E0UC[1] and WKPU[10].
49 PF[13] bidirectional GPIO PF[13] (S pad, tristate at reset) also carries E1UC[26], LIN5RX and WKPU[16].
50 PA[14] bidirectional GPIO PA[14] (M pad, tristate at reset) also carries SCK_0 and CS0_0 (DSPI_0), E0UC[0] and EIRQ[4].
51 PA[4] bidirectional GPIO PA[4] (S pad, tristate at reset) also carries E0UC[4], CS0_1 (DSPI_1), LIN5RX and WKPU[9].
52 PA[13] bidirectional GPIO PA[13] (M pad, tristate at reset) also carries SOUT_0 (DSPI_0) and E0UC[29].
53 PA[12] bidirectional GPIO PA[12] (S pad, tristate at reset) also carries E0UC[28], CS3_1 (DSPI_1), EIRQ[17] and SIN_0 (DSPI_0).
54 VDD_LV power_in 1.2 V regulator decoupling pin; a decoupling capacitor must be connected between this pin and the nearest VSS_LV pin.
55 VSS_LV power_in 1.2 V regulator decoupling pin; a decoupling capacitor must be connected between this pin and the nearest VDD_LV pin.
56 XTAL input Analog input of the fast oscillator amplifier; must be grounded if oscillator bypass mode is used.
57 VSS_HV power_in Digital ground.
58 EXTAL bidirectional Analog output of the oscillator amplifier when not in bypass mode; analog input for the clock generator when the oscillator is in bypass mode.
59 VDD_HV power_in Digital supply voltage (high-voltage domain).
60 PB[9] input Input-only PB[9] (OSC32K_EXTAL, ADC0_S[1], ADC1_S[5], WKPU[26]); PCR.IBE must be 0 for the oscillator function and this wakeup input cannot exit STANDBY.
61 PB[8] input Input-only PB[8] (OSC32K_XTAL, ADC0_S[0], ADC1_S[4], WKPU[25]); PCR.IBE must be 0 for the oscillator function and this wakeup input cannot exit STANDBY.
62 PB[10] bidirectional GPIO PB[10] (J pad, tristate at reset, analog feature) also carries WKPU[8], ADC0_S[2] and ADC1_S[6].
63 PF[0] bidirectional GPIO PF[0] (J pad, tristate at reset, analog feature) also carries E0UC[10], CS3_1 (DSPI_1) and ADC0_S[8].
64 PF[1] bidirectional GPIO PF[1] (J pad, tristate at reset, analog feature) also carries E0UC[11], CS4_1 (DSPI_1) and ADC0_S[9].
65 PF[2] bidirectional GPIO PF[2] (J pad, tristate at reset, analog feature) also carries E0UC[12], CS0_2 (DSPI_2) and ADC0_S[10].
66 PF[3] bidirectional GPIO PF[3] (J pad, tristate at reset, analog feature) also carries E0UC[13], CS1_2 (DSPI_2) and ADC0_S[11].
67 PF[4] bidirectional GPIO PF[4] (J pad, tristate at reset, analog feature) also carries E0UC[14], CS2_2 (DSPI_2) and ADC0_S[12].
68 PF[5] bidirectional GPIO PF[5] (J pad, tristate at reset, analog feature) also carries E0UC[22], CS3_2 (DSPI_2) and ADC0_S[13].
69 PF[6] bidirectional GPIO PF[6] (J pad, tristate at reset, analog feature) also carries E0UC[23], CS1_1 (DSPI_1) and ADC0_S[14].
70 PF[7] bidirectional GPIO PF[7] (J pad, tristate at reset, analog feature) also carries CS2_1 (DSPI_1) and ADC0_S[15].
71 PJ[3] bidirectional GPIO PJ[3] (J pad, tristate at reset, analog feature) also carries CS1_5 (DSPI_5) and ADC0_S[27].
72 PJ[2] bidirectional GPIO PJ[2] (J pad, tristate at reset, analog feature) also carries CS0_5 (DSPI_5) and ADC0_S[26].
73 PJ[1] bidirectional GPIO PJ[1] (J pad, tristate at reset, analog feature) also carries SIN_5 (DSPI_5) and ADC0_S[25].
74 PJ[0] bidirectional GPIO PJ[0] (J pad, tristate at reset, analog feature) also carries CS1_4 (DSPI_4) and ADC0_S[24].
75 PI[15] bidirectional GPIO PI[15] (J pad, tristate at reset, analog feature) also carries CS0_4 (DSPI_4) and ADC0_S[23].
76 PI[14] bidirectional GPIO PI[14] (J pad, tristate at reset, analog feature) also carries SIN_4 (DSPI_4) and ADC0_S[22].
77 PD[0] input Analog-capable input PD[0] (ADC0_P[4], ADC1_P[4], WKPU[27]), tristate at reset.
78 PD[1] input Analog-capable input PD[1] (ADC0_P[5], ADC1_P[5], WKPU[28]), tristate at reset.
79 PD[2] input Analog-capable input PD[2] (ADC0_P[6], ADC1_P[6]), tristate at reset.
80 PD[3] input Analog-capable input PD[3] (ADC0_P[7], ADC1_P[7]), tristate at reset.
81 PD[4] input Analog-capable input PD[4] (ADC0_P[8], ADC1_P[8]), tristate at reset.
82 PD[5] input Analog-capable input PD[5] (ADC0_P[9], ADC1_P[9]), tristate at reset.
83 PD[6] input Analog-capable input PD[6] (ADC0_P[10], ADC1_P[10]), tristate at reset.
84 PD[7] input Analog-capable input PD[7] (ADC0_P[11], ADC1_P[11]), tristate at reset.
85 VDD_HV power_in Digital supply voltage (high-voltage domain).
86 VSS_HV power_in Digital ground.
87 PD[8] input Analog-capable input PD[8] (ADC0_P[12], ADC1_P[12]), tristate at reset.
88 PB[4] input Analog-capable input PB[4] (ADC0_P[0], ADC1_P[0], GPIO[20]), tristate at reset.
89 VSS_HV_ADC0 power_in Reference ground and analog ground for the 10-bit ADC_0.
90 VDD_HV_ADC0 power_in Reference voltage and analog supply for the 10-bit ADC_0.
91 PB[5] input Analog-capable input PB[5] (ADC0_P[1], ADC1_P[1], GPIO[21]), tristate at reset.
92 PB[6] input Analog-capable input PB[6] (ADC0_P[2], ADC1_P[2], GPIO[22]), tristate at reset.
93 PB[7] input Analog-capable input PB[7] (ADC0_P[3], ADC1_P[3], GPIO[23]), tristate at reset.
94 PD[9] input Analog-capable input PD[9] (ADC0_P[13], ADC1_P[13]), tristate at reset.
95 PD[10] input Analog-capable input PD[10] (ADC0_P[14], ADC1_P[14]), tristate at reset.
96 PD[11] input Analog-capable input PD[11] (ADC0_P[15], ADC1_P[15]), tristate at reset.
97 PB[11] bidirectional GPIO PB[11] (J pad, tristate at reset, analog feature) also carries E0UC[3], CS0_0 (DSPI_0) and ADC0_S[3]; available in LQFP176 only.
98 VSS_HV_ADC1 power_in Reference ground and analog ground for the 12-bit ADC_1.
99 VDD_HV_ADC1 power_in Reference voltage and analog supply for the 12-bit ADC_1.
100 PD[12] bidirectional GPIO PD[12] (J pad, tristate at reset, analog feature) also carries CS5_0 (DSPI_0), E0UC[24] and ADC0_S[4]; available in LQFP176 only.
101 PB[12] bidirectional GPIO PB[12] (J pad, tristate at reset, analog feature) also carries E0UC[4], CS1_0 (DSPI_0) and ADC0_X[0].
102 PD[13] bidirectional GPIO PD[13] (J pad, tristate at reset, analog feature) also carries CS0_1 (DSPI_1), E0UC[25] and ADC0_S[5].
103 PB[13] bidirectional GPIO PB[13] (J pad, tristate at reset, analog feature) also carries E0UC[5], CS2_0 (DSPI_0) and ADC0_X[1].
104 PD[14] bidirectional GPIO PD[14] (J pad, tristate at reset, analog feature) also carries CS1_1 (DSPI_1), E0UC[26] and ADC0_S[6].
105 PB[14] bidirectional GPIO PB[14] (J pad, tristate at reset, analog feature) also carries E0UC[6], CS3_0 (DSPI_0) and ADC0_X[2].
106 PD[15] bidirectional GPIO PD[15] (J pad, tristate at reset, analog feature) also carries CS2_1 (DSPI_1), E0UC[27] and ADC0_S[7].
107 PB[15] bidirectional GPIO PB[15] (J pad, tristate at reset, analog feature) also carries E0UC[7], CS4_0 (DSPI_0) and ADC0_X[3].
108 PI[8] bidirectional GPIO PI[8] (J pad, tristate at reset, analog feature) also carries ADC0_S[16].
109 PI[9] bidirectional GPIO PI[9] (J pad, tristate at reset, analog feature) also carries ADC0_S[17].
110 PI[10] bidirectional GPIO PI[10] (J pad, tristate at reset, analog feature) also carries ADC0_S[18].
111 PI[11] bidirectional GPIO PI[11] (J pad, tristate at reset, analog feature) also carries SIN_3 (DSPI_3) and ADC0_S[19].
112 PI[12] bidirectional GPIO PI[12] (J pad, tristate at reset, analog feature) also carries CS0_3 (DSPI_3) and ADC0_S[20].
113 PI[13] bidirectional GPIO PI[13] (J pad, tristate at reset, analog feature) also carries CS1_3 (DSPI_3) and ADC0_S[21].
114 PA[3] bidirectional GPIO PA[3] (J pad, tristate at reset, analog feature) also carries LIN5TX, E0UC[3], CS4_1 (DSPI_1), EIRQ[0] and ADC1_S[0].
115 PG[13] bidirectional GPIO PG[13] (M pad, tristate at reset) also carries E0UC[27] and SCK_4 (DSPI_4).
116 PG[12] bidirectional GPIO PG[12] (M pad, tristate at reset) also carries E0UC[26] and SOUT_4 (DSPI_4).
117 PH[0] bidirectional GPIO PH[0] (M pad, tristate at reset) also carries E1UC[2] and SIN_1 (DSPI_1).
118 PH[1] bidirectional GPIO PH[1] (M pad, tristate at reset) also carries E1UC[3] and SOUT_1 (DSPI_1).
119 PH[2] bidirectional GPIO PH[2] (M pad, tristate at reset) also carries E1UC[4] and SCK_1 (DSPI_1).
120 PH[3] bidirectional GPIO PH[3] (M pad, tristate at reset) also carries E1UC[5] and CS0_1 (DSPI_1).
121 PG[1] bidirectional GPIO PG[1] (S pad, tristate at reset) also carries E1UC[24], EIRQ[14] and CAN5RX.
122 PG[0] bidirectional GPIO PG[0] (M pad, tristate at reset) also carries CAN5TX and E1UC[23].
123 VSS_HV power_in Digital ground.
124 VDD_HV power_in Digital supply voltage (high-voltage domain).
125 PF[15] bidirectional GPIO PF[15] (S pad, tristate at reset) also carries E1UC[4], EIRQ[13], CAN1RX and CAN4RX.
126 PF[14] bidirectional GPIO PF[14] (M pad, tristate at reset) also carries CAN4TX, E1UC[27] and CAN1TX.
127 PE[13] bidirectional GPIO PE[13] (S pad, tristate at reset) also carries SOUT_2 (DSPI_2) and E1UC[20].
128 PA[7] bidirectional GPIO PA[7] (J pad, tristate at reset, analog feature) also carries E0UC[7], LIN3TX, EIRQ[2] and ADC1_S[1].
129 PA[8] input GPIO PA[8] (S pad) with input weak pull-up out of reset; also carries E0UC[8], E0UC[14], EIRQ[3], ABS[0] and LIN3RX.
130 PA[9] bidirectional GPIO PA[9] (S pad) is pull-down at reset (FAB); without an external strong pull-up the device starts fetching from flash; also carries E0UC[9] and CS2_1 (DSPI_1).
131 PA[10] bidirectional GPIO PA[10] (J pad, tristate at reset, analog feature) also carries E0UC[10], SDA (I2C_0), LIN2TX and ADC1_S[2].
132 PA[11] bidirectional GPIO PA[11] (J pad, tristate at reset, analog feature) also carries E0UC[11], SCL (I2C_0), EIRQ[16], LIN2RX and ADC1_S[3].
133 PE[12] bidirectional GPIO PE[12] (J pad, tristate at reset, analog feature) also carries E1UC[19], SIN_2 (DSPI_2), EIRQ[11] and ADC1_S[7].
134 PG[14] bidirectional GPIO PG[14] (S pad, tristate at reset) also carries E1UC[0] and LIN8TX.
135 PG[15] bidirectional GPIO PG[15] (M pad, tristate at reset) also carries E1UC[1] and LIN8RX.
136 PE[14] bidirectional GPIO PE[14] (S pad, tristate at reset) also carries SCK_2 (DSPI_2), E1UC[21] and EIRQ[12].
137 PE[15] bidirectional GPIO PE[15] (M pad, tristate at reset) also carries CS0_2 (DSPI_2) and E1UC[22].
138 PG[10] bidirectional GPIO PG[10] (S pad, tristate at reset) also carries E0UC[24], E1UC[31] and SIN_4 (DSPI_4).
139 PG[11] bidirectional GPIO PG[11] (M pad, tristate at reset) also carries E0UC[25] and CS0_4 (DSPI_4).
140 PH[11] bidirectional GPIO PH[11] (M pad, tristate at reset) also carries SOUT_3 (DSPI_3), CS0_4 (DSPI_4) and E1UC[5]; available in LQFP176 only.
141 PH[12] bidirectional GPIO PH[12] (M pad, tristate at reset) also carries SCK_3 (DSPI_3), CS1_4 (DSPI_4) and E1UC[25]; available in LQFP176 only.
142 PI[5] bidirectional GPIO PI[5] (S pad, tristate at reset) also carries E1UC[29] and SCK_4 (DSPI_4).
143 PI[4] bidirectional GPIO PI[4] (S pad, tristate at reset) also carries E1UC[28] and SOUT_4 (DSPI_4).
144 PC[3] bidirectional GPIO PC[3] (S pad, tristate at reset) also carries CS0_1 (DSPI_1), MA[0] (ADC_0), DEBUG[1], EIRQ[6], CAN1RX and CAN4RX.
145 PC[2] bidirectional GPIO PC[2] (M pad, tristate at reset) also carries SCK_1 (DSPI_1), CAN4TX, DEBUG[0] and EIRQ[5].
146 PA[5] bidirectional GPIO PA[5] (M pad, tristate at reset) also carries E0UC[5] and LIN4TX.
147 PA[6] bidirectional GPIO PA[6] (S pad, tristate at reset) also carries E0UC[6], CS1_1 (DSPI_1), EIRQ[1] and LIN4RX.
148 PH[10] input PH[10] (M pad) with input weak pull-up out of reset; functions as TMS (JTAGC) unless configured as GPIO.
149 PC[1] bidirectional PC[1] (F pad, medium configuration by default) is TDO in alternate function 2 after reset; it is only available as GPIO after reconfiguration.
150 VSS_HV power_in Digital ground.
151 VDD_HV power_in Digital supply voltage (high-voltage domain).
152 VDD_LV power_in 1.2 V regulator decoupling pin; a decoupling capacitor must be connected between this pin and the nearest VSS_LV pin.
153 VSS_LV power_in 1.2 V regulator decoupling pin; a decoupling capacitor must be connected between this pin and the nearest VDD_LV pin.
154 PC[0] bidirectional PC[0] (M pad) with input weak pull-up out of reset; functions as TDI (JTAGC) unless configured as GPIO.
155 PH[9] input PH[9] (S pad) with input weak pull-up out of reset; functions as TCK (JTAGC) unless configured as GPIO.
156 PE[2] bidirectional GPIO PE[2] (M pad, tristate at reset) also carries E0UC[18], EIRQ[21] and SIN_1 (DSPI_1).
157 PE[3] bidirectional GPIO PE[3] (M pad, tristate at reset) also carries E0UC[19] and SOUT_1 (DSPI_1).
158 PC[5] bidirectional GPIO PC[5] (M pad, tristate at reset) also carries SOUT_1 (DSPI_1), CAN3TX, DEBUG[3] and EIRQ[7].
159 PC[4] bidirectional GPIO PC[4] (M pad, tristate at reset) also carries E1UC[31], SIN_1 (DSPI_1), CAN3RX, DEBUG[2] and EIRQ[18].
160 PE[4] bidirectional GPIO PE[4] (M pad, tristate at reset) also carries E0UC[20], SCK_1 (DSPI_1) and EIRQ[9].
161 PE[5] bidirectional GPIO PE[5] (M pad, tristate at reset) also carries E0UC[21], CS0_1 (DSPI_1) and MA[2] (ADC_0).
162 PH[4] bidirectional GPIO PH[4] (M pad, tristate at reset) also carries E1UC[6].
163 PH[5] bidirectional GPIO PH[5] (S pad, tristate at reset) also carries E1UC[7].
164 PH[6] bidirectional GPIO PH[6] (M pad, tristate at reset) also carries E1UC[8] and MA[2] (ADC_0).
165 PH[7] bidirectional GPIO PH[7] (M pad, tristate at reset) also carries E1UC[9], CS3_2 (DSPI_2) and MA[1] (ADC_0).
166 PH[8] bidirectional GPIO PH[8] (M pad, tristate at reset) also carries E1UC[10], CS2_2 (DSPI_2) and MA[0] (ADC_0).
167 PE[6] bidirectional GPIO PE[6] (M pad, tristate at reset) also carries E0UC[22], CS3_0 (DSPI_0), MA[1] (ADC_0) and EIRQ[22].
168 PE[7] bidirectional GPIO PE[7] (M pad, tristate at reset) also carries E0UC[23], CS2_0 (DSPI_0), MA[0] (ADC_0) and EIRQ[23].
169 PI[3] bidirectional GPIO PI[3] (S pad, tristate at reset) also carries E0UC[31], WKPU[23] and LIN9RX; available in LQFP176 only.
170 PI[2] bidirectional GPIO PI[2] (S pad, tristate at reset) also carries E0UC[30] and LIN9TX; available in LQFP176 only.
171 PI[1] bidirectional GPIO PI[1] (S pad, tristate at reset) also carries E0UC[29], WKPU[24] and LIN8RX; available in LQFP176 only.
172 PI[0] bidirectional GPIO PI[0] (S pad, tristate at reset) also carries E0UC[28] and LIN8TX; available in LQFP176 only.
173 PC[12] bidirectional GPIO PC[12] (M pad, tristate at reset) also carries E0UC[12], EIRQ[19] and SIN_2 (DSPI_2).
174 PC[13] bidirectional GPIO PC[13] (S pad, tristate at reset) also carries E0UC[13] and SOUT_2 (DSPI_2).
175 PC[8] bidirectional GPIO PC[8] (S pad, tristate at reset) also carries LIN2TX, E0UC[3] and DEBUG[6].
176 PB[2] bidirectional GPIO PB[2] (M pad, tristate at reset) also carries LIN0TX, SDA (I2C_0) and E0UC[30].

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-176(24x24)
Category Embedded Processors & Controllers
Pins 176

CAD (KiCad official)

  • Symbol: SPC560B64L7C6E0X
  • Footprint: Package_QFP:LQFP-176_24x24mm_P0.5mm
  • 3D model: LQFP-176(24x24) (KiCad packages3D, STEP)
  • 3D model files: spc560b64l7c6e0x-etched.step / spc560b64l7c6e0x-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); spc560b64l7c6e0x.step / spc560b64l7c6e0x.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (133 pp, sha256 0e637f7c66580983, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF