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SPC560B54L3C6E0X

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersspc560b54l3c6e0xfactory-2.0.0extractor-text
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Contents

README

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SPC560B54L3C6E0X

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

SPC560B54L3C6E0X from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB[3] bidirectional GPIO PB[3] (PCR[19]), S-type pad, tristate after reset; alternate functions E0UC[31], SCL (I2C_0), WKPU[11] wakeup and LIN0RX (LINFlex_0).
2 PC[9] bidirectional GPIO PC[9] (PCR[41]), S-type pad, tristate after reset; alternate functions E0UC[7], DEBUG[7], WKPU[13] wakeup and LIN2RX (LINFlex_2).
3 PC[14] bidirectional GPIO PC[14] (PCR[46]), S-type pad, tristate after reset; alternate functions E0UC[14], SCK_2 (DSPI_2) and EIRQ[8].
4 PC[15] bidirectional GPIO PC[15] (PCR[47]), M-type pad, tristate after reset; alternate functions E0UC[15], CS0_2 (DSPI_2) and EIRQ[20].
5 PA[2] bidirectional GPIO PA[2] (PCR[2]), S-type pad, tristate after reset; alternate functions E0UC[2], MA[2] (ADC_0) and WKPU[3] wakeup.
6 PE[0] bidirectional GPIO PE[0] (PCR[64]), S-type pad, tristate after reset; alternate functions E0UC[16], CAN5RX (FlexCAN_5) and WKPU[6] wakeup.
7 PA[1] bidirectional GPIO PA[1] (PCR[1]), S-type pad, tristate after reset; alternate functions E0UC[1], NMI (higher priority than the alternate function when selected) and WKPU[2] wakeup.
8 PE[1] bidirectional GPIO PE[1] (PCR[65]), M-type pad, tristate after reset; alternate functions E0UC[17] and CAN5TX (FlexCAN_5).
9 PE[8] bidirectional GPIO PE[8] (PCR[72]), M-type pad, tristate after reset; alternate functions CAN2TX (FlexCAN_2), E0UC[22] and CAN3TX (FlexCAN_3).
10 PE[9] bidirectional GPIO PE[9] (PCR[73]), S-type pad, tristate after reset; alternate functions E0UC[23], CAN2RX/CAN3RX (FlexCAN_2/3) and WKPU[7] wakeup.
11 PE[10] bidirectional GPIO PE[10] (PCR[74]), S-type pad, tristate after reset; alternate functions LIN3TX (LINFlex_3), CS3_1 (DSPI_1), E1UC[30] and EIRQ[10].
12 PA[0] bidirectional GPIO PA[0] (PCR[0]), M-type pad, tristate after reset; alternate functions E0UC[0], CLKOUT (MC_CGM), E0UC[13] and WKPU[19] wakeup.
13 PE[11] bidirectional GPIO PE[11] (PCR[75]), S-type pad, tristate after reset; alternate functions E0UC[24], CS4_1 (DSPI_1), LIN3RX (LINFlex_3) and WKPU[14] wakeup.
14 VSS_HV power_in Digital ground for the high-voltage supply domain.
15 VDD_HV power_in Digital supply for the high-voltage domain; the value is 5.0 V or 3.3 V as selected by NVUSRO[PAD3V5V].
16 VSS_HV power_in Digital ground for the high-voltage supply domain.
17 RESET bidirectional Bidirectional reset with Schmitt-trigger characteristics and noise filter; the device drives it low until 40 FIRC clock cycles after phase 2 completion.
18 VSS_LV power_in 1.2 V regulator ground; a decoupling capacitor must be connected between this pin and the nearest VDD_LV pin.
19 VDD_LV power_in 1.2 V regulator supply; a decoupling capacitor must be connected between this pin and the nearest VSS_LV pin.
20 VDD_BV power_in Internal regulator supply voltage input.
21 PC[11] bidirectional GPIO PC[11] (PCR[43]), S-type pad, tristate after reset; alternate functions MA[2] (ADC_0), WKPU[5] wakeup, CAN1RX and CAN4RX (FlexCAN_1/4).
22 PC[10] bidirectional GPIO PC[10] (PCR[42]), M-type pad, tristate after reset; alternate functions CAN1TX and CAN4TX (FlexCAN_1/4) and MA[1] (ADC_0).
23 PB[0] bidirectional GPIO PB[0] (PCR[16]), M-type pad, tristate after reset; alternate functions CAN0TX (FlexCAN_0), E0UC[30] and LIN0TX (LINFlex_0).
24 PB[1] bidirectional GPIO PB[1] (PCR[17]), S-type pad, tristate after reset; alternate functions E0UC[31], CAN0RX and LIN0RX (FlexCAN_0/LINFlex_0) and WKPU[4] wakeup.
25 PC[6] bidirectional GPIO PC[6] (PCR[38]), S-type pad, tristate after reset; alternate functions LIN1TX (LINFlex_1), E1UC[28] and DEBUG[4].
26 PC[7] bidirectional GPIO PC[7] (PCR[39]), S-type pad, tristate after reset; alternate functions E1UC[29], DEBUG[5], LIN1RX (LINFlex_1) and WKPU[12] wakeup.
27 PA[15] bidirectional GPIO PA[15] (PCR[15]), M-type pad, tristate after reset; alternate functions CS0_0 and SCK_0 (DSPI_0), E0UC[1] and WKPU[10] wakeup.
28 PA[14] bidirectional GPIO PA[14] (PCR[14]), M-type pad, tristate after reset; alternate functions SCK_0 and CS0_0 (DSPI_0), E0UC[0] and EIRQ[4].
29 PA[4] bidirectional GPIO PA[4] (PCR[4]), S-type pad, tristate after reset; alternate functions E0UC[4], CS0_1 (DSPI_1), LIN5RX (LINFlex_5) and WKPU[9] wakeup.
30 PA[13] bidirectional GPIO PA[13] (PCR[13]), M-type pad, tristate after reset; alternate functions SOUT_0 (DSPI_0) and E0UC[29].
31 PA[12] bidirectional GPIO PA[12] (PCR[12]), S-type pad, tristate after reset; alternate functions E0UC[28], CS3_1 (DSPI_1), SIN_0 (DSPI_0) and EIRQ[17].
32 VDD_LV power_in 1.2 V regulator supply; a decoupling capacitor must be connected between this pin and the nearest VSS_LV pin.
33 VSS_LV power_in 1.2 V regulator ground; a decoupling capacitor must be connected between this pin and the nearest VDD_LV pin.
34 XTAL input Analog input of the oscillator amplifier circuit; it must be grounded if oscillator bypass mode is used.
35 VSS_HV power_in Digital ground for the high-voltage supply domain.
36 EXTAL bidirectional Analog output of the oscillator amplifier when not in bypass mode; analog input for the clock generator when the oscillator is in bypass mode.
37 VDD_HV power_in Digital supply for the high-voltage domain; the value is 5.0 V or 3.3 V as selected by NVUSRO[PAD3V5V].
38 PB[9] input Input-only analog pad PB[9] (PCR[25]) with alternate functions OSC32K_EXTAL (32 kHz oscillator), ADC0_S[1] and ADC1_S[5]; it cannot be used to exit STANDBY mode.
39 PB[8] input Input-only analog pad PB[8] (PCR[24]) with alternate functions OSC32K_XTAL (32 kHz oscillator), WKPU[25] wakeup, ADC0_S[0] and ADC1_S[4]; it cannot be used to exit STANDBY mode.
40 PB[10] bidirectional J-type I/O pad PB[10] (PCR[26]) with analog feature, tristate after reset; alternate functions WKPU[8] wakeup, ADC0_S[2] and ADC1_S[6].
41 PD[0] input Input-only analog pad PD[0] (PCR[48]) with alternate functions WKPU[27] wakeup, ADC0_P[4] and ADC1_P[4].
42 PD[1] input Input-only analog pad PD[1] (PCR[49]) with alternate functions WKPU[28] wakeup, ADC0_P[5] and ADC1_P[5].
43 PD[2] input Input-only analog pad PD[2] (PCR[50]) with analog alternate functions ADC0_P[6] and ADC1_P[6].
44 PD[3] input Input-only analog pad PD[3] (PCR[51]) with analog alternate functions ADC0_P[7] and ADC1_P[7].
45 PD[4] input Input-only analog pad PD[4] (PCR[52]) with analog alternate functions ADC0_P[8] and ADC1_P[8].
46 PD[5] input Input-only analog pad PD[5] (PCR[53]) with analog alternate functions ADC0_P[9] and ADC1_P[9].
47 PD[6] input Input-only analog pad PD[6] (PCR[54]) with analog alternate functions ADC0_P[10] and ADC1_P[10].
48 PD[7] input Input-only analog pad PD[7] (PCR[55]) with analog alternate functions ADC0_P[11] and ADC1_P[11].
49 PD[8] input Input-only analog pad PD[8] (PCR[56]) with analog alternate functions ADC0_P[12] and ADC1_P[12].
50 PB[4] input Input-only analog pad PB[4] (PCR[20]) with analog alternate functions ADC0_P[0] and ADC1_P[0].
51 VSS_HV_ADC0 power_in Reference and analog ground for the 10-bit ADC_0.
52 VDD_HV_ADC0 power_in Reference voltage and analog supply for the 10-bit ADC_0.
53 PB[5] input Input-only analog pad PB[5] (PCR[21]) with analog alternate functions ADC0_P[1] and ADC1_P[1].
54 PB[6] input Input-only analog pad PB[6] (PCR[22]) with analog alternate functions ADC0_P[2] and ADC1_P[2].
55 PB[7] input Input-only analog pad PB[7] (PCR[23]) with analog alternate functions ADC0_P[3] and ADC1_P[3].
56 PD[9] input Input-only analog pad PD[9] (PCR[57]) with analog alternate functions ADC0_P[13] and ADC1_P[13].
57 PD[10] input Input-only analog pad PD[10] (PCR[58]) with analog alternate functions ADC0_P[14] and ADC1_P[14].
58 PD[11] input Input-only analog pad PD[11] (PCR[59]) with analog alternate functions ADC0_P[15] and ADC1_P[15].
59 VSS_HV_ADC1 power_in Reference and analog ground for the 12-bit ADC_1.
60 VDD_HV_ADC1 power_in Reference voltage and analog supply for the 12-bit ADC_1.
61 PB[12] bidirectional J-type I/O pad PB[12] (PCR[28]) with analog feature; alternate functions E0UC[4], CS1_0 (DSPI_0) and ADC0_X[0].
62 PD[13] bidirectional J-type I/O pad PD[13] (PCR[61]) with analog feature; alternate functions CS0_1 (DSPI_1), E0UC[25] and ADC0_S[5].
63 PB[13] bidirectional J-type I/O pad PB[13] (PCR[29]) with analog feature; alternate functions E0UC[5], CS2_0 (DSPI_0) and ADC0_X[1].
64 PD[14] bidirectional J-type I/O pad PD[14] (PCR[62]) with analog feature; alternate functions CS1_1 (DSPI_1), E0UC[26] and ADC0_S[6].
65 PB[14] bidirectional J-type I/O pad PB[14] (PCR[30]) with analog feature; alternate functions E0UC[6], CS3_0 (DSPI_0) and ADC0_X[2].
66 PD[15] bidirectional J-type I/O pad PD[15] (PCR[63]) with analog feature; alternate functions CS2_1 (DSPI_1), E0UC[27] and ADC0_S[7].
67 PB[15] bidirectional J-type I/O pad PB[15] (PCR[31]) with analog feature; alternate functions E0UC[7], CS4_0 (DSPI_0) and ADC0_X[3].
68 PA[3] bidirectional J-type I/O pad PA[3] (PCR[3]) with analog feature; alternate functions E0UC[3], LIN5TX (LINFlex_5), CS4_1 (DSPI_1), EIRQ[0] and ADC1_S[0].
69 VSS_HV power_in Digital ground for the high-voltage supply domain.
70 VDD_HV power_in Digital supply for the high-voltage domain; the value is 5.0 V or 3.3 V as selected by NVUSRO[PAD3V5V].
71 PA[7] bidirectional J-type I/O pad PA[7] (PCR[7]) with analog feature, tristate after reset; alternate functions E0UC[7], LIN3TX (LINFlex_3), EIRQ[2] and ADC1_S[1].
72 PA[8] bidirectional S-type pad PA[8] (PCR[8]), input with weak pull-up out of reset; alternate functions E0UC[8], E0UC[14], EIRQ[3], ABS[0] (BAM) and LIN3RX (LINFlex_3).
73 PA[9] bidirectional S-type pad PA[9] (PCR[9]) with FAB function, pull-down out of reset; without an external strong pull-up the device starts fetching from flash.
74 PA[10] bidirectional J-type I/O pad PA[10] (PCR[10]) with analog feature, tristate after reset; alternate functions E0UC[10], SDA (I2C_0), LIN2TX (LINFlex_2) and ADC1_S[2].
75 PA[11] bidirectional J-type I/O pad PA[11] (PCR[11]) with analog feature, tristate after reset; alternate functions E0UC[11], SCL (I2C_0), EIRQ[16], LIN2RX (LINFlex_2) and ADC1_S[3].
76 PE[12] bidirectional J-type I/O pad PE[12] (PCR[76]) with analog feature, tristate after reset; alternate functions SIN_2 (DSPI_2), EIRQ[11] and ADC1_S[7]; E1UC[19] is not available on LQFP100.
77 PC[3] bidirectional S-type I/O pad PC[3] (PCR[35]), tristate after reset; alternate functions CS0_1 (DSPI_1), MA[0] (ADC_0), DEBUG[1], EIRQ[6], CAN1RX and CAN4RX (FlexCAN_1/4).
78 PC[2] bidirectional M-type I/O pad PC[2] (PCR[34]), tristate after reset; alternate functions SCK_1 (DSPI_1), CAN4TX (FlexCAN_4), DEBUG[0] and EIRQ[5].
79 PA[5] bidirectional M-type I/O pad PA[5] (PCR[5]), tristate after reset; alternate functions E0UC[5] and LIN4TX (LINFlex_4).
80 PA[6] bidirectional S-type I/O pad PA[6] (PCR[6]), tristate after reset; alternate functions E0UC[6], CS1_1 (DSPI_1), EIRQ[1] and LIN4RX (LINFlex_4).
81 PH[10] input M-type pad PH[10] (PCR[122]), input with weak pull-up out of reset; it is the TMS JTAG input and can be configured as GPIO by the user.
82 PC[1] output Fast/medium pad PC[1] (PCR[33]) in medium configuration by default; after reset it carries the TDO JTAG output in AF2 mode and can be reconfigured as GPIO.
83 VSS_HV power_in Digital ground for the high-voltage supply domain.
84 VDD_HV power_in Digital supply for the high-voltage domain; the value is 5.0 V or 3.3 V as selected by NVUSRO[PAD3V5V].
85 VDD_LV power_in 1.2 V regulator supply; a decoupling capacitor must be connected between this pin and the nearest VSS_LV pin.
86 VSS_LV power_in 1.2 V regulator ground; a decoupling capacitor must be connected between this pin and the nearest VDD_LV pin.
87 PC[0] input M-type pad PC[0] (PCR[32]), input with weak pull-up out of reset; it is the TDI JTAG input and can be configured as GPIO by the user.
88 PH[9] input S-type pad PH[9] (PCR[121]), input with weak pull-up out of reset; it is the TCK JTAG input and can be configured as GPIO by the user.
89 PE[2] bidirectional M-type I/O pad PE[2] (PCR[66]), tristate after reset; alternate functions E0UC[18], SIN_1 (DSPI_1) and EIRQ[21].
90 PE[3] bidirectional M-type I/O pad PE[3] (PCR[67]), tristate after reset; alternate functions E0UC[19] and SOUT_1 (DSPI_1).
91 PC[5] bidirectional M-type I/O pad PC[5] (PCR[37]), tristate after reset; alternate functions SOUT_1 (DSPI_1), CAN3TX (FlexCAN_3), DEBUG[3] and EIRQ[7].
92 PC[4] bidirectional M-type I/O pad PC[4] (PCR[36]), tristate after reset; alternate functions E1UC[31], DEBUG[2], EIRQ[18], SIN_1 (DSPI_1) and CAN3RX (FlexCAN_3).
93 PE[4] bidirectional M-type I/O pad PE[4] (PCR[68]), tristate after reset; alternate functions E0UC[20], SCK_1 (DSPI_1) and EIRQ[9].
94 PE[5] bidirectional M-type I/O pad PE[5] (PCR[69]), tristate after reset; alternate functions E0UC[21], CS0_1 (DSPI_1) and MA[2] (ADC_0).
95 PE[6] bidirectional M-type I/O pad PE[6] (PCR[70]), tristate after reset; alternate functions E0UC[22], CS3_0 (DSPI_0), MA[1] (ADC_0) and EIRQ[22].
96 PE[7] bidirectional M-type I/O pad PE[7] (PCR[71]), tristate after reset; alternate functions E0UC[23], CS2_0 (DSPI_0), MA[0] (ADC_0) and EIRQ[23].
97 PC[12] bidirectional M-type I/O pad PC[12] (PCR[44]), tristate after reset; alternate functions E0UC[12], EIRQ[19] and SIN_2 (DSPI_2).
98 PC[13] bidirectional S-type I/O pad PC[13] (PCR[45]), tristate after reset; alternate functions E0UC[13] and SOUT_2 (DSPI_2).
99 PC[8] bidirectional S-type I/O pad PC[8] (PCR[40]), tristate after reset; alternate functions LIN2TX (LINFlex_2), E0UC[3] and DEBUG[6].
100 PB[2] bidirectional M-type I/O pad PB[2] (PCR[18]), tristate after reset; alternate functions LIN0TX (LINFlex_0), SDA (I2C_0) and E0UC[30].

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: SPC560B54L3C6E0X
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: spc560b54l3c6e0x-etched.step / spc560b54l3c6e0x-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); spc560b54l3c6e0x.step / spc560b54l3c6e0x.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (133 pp, sha256 0e637f7c66580983, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF