# SPC560B50L5C6E0Y

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

SPC560B50L5C6E0Y from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PB[3] | bidirectional | Slow pad GPIO[19] with I2C_0 SCL (AF2), WKPU[11] wakeup input and LIN0RX input. |
| 2 | PC[9] | bidirectional | Slow pad GPIO[41] with LIN2RX input and WKPU[13] wakeup input. |
| 3 | PC[14] | bidirectional | Slow pad GPIO[46] with E0UC[14], DSPI_2 SCK_2 (AF2) and EIRQ[8] input. |
| 4 | PC[15] | bidirectional | Medium pad GPIO[47] with E0UC[15] and DSPI_2 CS0_2 (AF2). |
| 5 | PG[5] | bidirectional | Slow pad GPIO[101] with E1UC[14] and WKPU[18] wakeup input. |
| 6 | PG[4] | bidirectional | Medium pad GPIO[100] with E1UC[13]. |
| 7 | PG[3] | bidirectional | Slow pad GPIO[99] with E1UC[12] and WKPU[17] wakeup input. |
| 8 | PG[2] | bidirectional | Medium pad GPIO[98] with E1UC[11]. |
| 9 | PA[2] | bidirectional | Slow pad GPIO[2] with E0UC[2] and WKPU[3] wakeup input. |
| 10 | PE[0] | bidirectional | Slow pad GPIO[64] with E0UC[16], CAN5RX input and WKPU[6] wakeup input. |
| 11 | PA[1] | bidirectional | Slow pad GPIO[1] with E0UC[1], NMI input (higher priority than alternate function) and WKPU[2] wakeup input. |
| 12 | PE[1] | bidirectional | Medium pad GPIO[65] with E0UC[17] and CAN5TX output (AF2). |
| 13 | PE[8] | bidirectional | Medium pad GPIO[72] with CAN2TX, E0UC[22] and CAN3TX outputs. |
| 14 | PE[9] | bidirectional | Slow pad GPIO[73] with E0UC[23], CAN2RX/CAN3RX inputs and WKPU[7] wakeup input. |
| 15 | PE[10] | bidirectional | Slow pad GPIO[74] with LIN3TX, DSPI_1 CS3_1 and EIRQ[10] input. |
| 16 | PA[0] | bidirectional | Medium pad GPIO[0] with E0UC[0], CLKOUT output and WKPU[19] wakeup input. |
| 17 | PE[11] | bidirectional | Slow pad GPIO[75] with DSPI_1 CS4_1, LIN3RX input and WKPU[14] wakeup input. |
| 18 | VSS_HV | power_in | Digital ground. |
| 19 | VDD_HV | power_in | Digital supply voltage (3.0-3.6 V or 4.5-5.5 V), with 100 nF between each VDD/VSS pair. |
| 20 | VSS_HV | power_in | Digital ground. |
| 21 | RESET | bidirectional | Bidirectional reset with Schmitt-Trigger characteristics and noise filter, medium pad, weak pull-up only after PHASE2. |
| 22 | VSS_LV | power_in | 1.2 V decoupling pin; a 330 nF capacitor must be connected to the nearest VDD_LV pin. |
| 23 | VDD_LV | power_in | 1.2 V decoupling pin; a 330 nF capacitor must be connected to the nearest VSS_LV pin. |
| 24 | VDD_BV | power_in | Internal regulator supply voltage, aligned with VDD (3.0-3.6 V or 4.5-5.5 V), with 400 nF (3.3 V) or 100 nF (5 V) to the nearest VSS_LV. |
| 25 | PG[9] | bidirectional | Slow pad GPIO[105] with E1UC[18] and DSPI_2 SCK_2 (AF3). |
| 26 | PG[8] | bidirectional | Slow pad GPIO[104] with E1UC[17], DSPI_2 CS0_2 (AF3) and EIRQ[15] input. |
| 27 | PC[11] | bidirectional | Slow pad GPIO[43] with CAN1RX/CAN4RX inputs and WKPU[5] wakeup input. |
| 28 | PC[10] | bidirectional | Medium pad GPIO[42] with CAN1TX, CAN4TX and ADC MA[1] outputs. |
| 29 | PG[7] | bidirectional | Medium pad GPIO[103] with E1UC[16]. |
| 30 | PG[6] | bidirectional | Medium pad GPIO[102] with E1UC[15]. |
| 31 | PB[0] | bidirectional | Medium pad GPIO[16] with CAN0TX output. |
| 32 | PB[1] | bidirectional | Slow pad GPIO[17] with WKPU[4] wakeup input and CAN0RX input. |
| 33 | PF[9] | bidirectional | Slow pad GPIO[89] with DSPI_0 CS5_0 and CAN2RX/CAN3RX inputs. |
| 34 | PF[8] | bidirectional | Medium pad GPIO[88] with CAN3TX, DSPI_0 CS4_0 and CAN2TX. |
| 35 | PF[12] | bidirectional | Medium pad GPIO[92] with E1UC[25]. |
| 36 | PC[6] | bidirectional | Slow pad GPIO[38] with LIN1TX output. |
| 37 | PC[7] | bidirectional | Slow pad GPIO[39] with LIN1RX input and WKPU[12] wakeup input. |
| 38 | PF[10] | bidirectional | Medium pad GPIO[90]. |
| 39 | PF[11] | bidirectional | Slow pad GPIO[91] with WKPU[15] wakeup input. |
| 40 | PA[15] | bidirectional | Medium pad GPIO[15] with DSPI_0 CS0_0, SCK_0 and WKPU[10] wakeup input. |
| 41 | PF[13] | bidirectional | Slow pad GPIO[93] with E1UC[26] and WKPU[16] wakeup input. |
| 42 | PA[14] | bidirectional | Medium pad GPIO[14] with DSPI_0 SCK_0, CS0_0 and EIRQ[4] input. |
| 43 | PA[4] | bidirectional | Slow pad GPIO[4] with E0UC[4] and WKPU[9] wakeup input. |
| 44 | PA[13] | bidirectional | Medium pad GPIO[13] with DSPI_0 SOUT_0 output. |
| 45 | PA[12] | bidirectional | Slow pad GPIO[12] with DSPI_0 SIN_0 input. |
| 46 | VDD_LV | power_in | 1.2 V decoupling pin; a 330 nF capacitor must be connected to the nearest VSS_LV pin. |
| 47 | VSS_LV | power_in | 1.2 V decoupling pin; a 330 nF capacitor must be connected to the nearest VDD_LV pin. |
| 48 | XTAL | input | Analog input of the oscillator amplifier circuit; must be grounded if the oscillator is used in bypass mode. |
| 49 | VSS_HV | power_in | Digital ground. |
| 50 | EXTAL | bidirectional | Analog output of the oscillator amplifier, or analog clock input when the oscillator is in bypass mode. |
| 51 | VDD_HV | power_in | Digital supply voltage (3.0-3.6 V or 4.5-5.5 V), with 100 nF between each VDD/VSS pair. |
| 52 | PB[9] | input | Input-only pad GPIO[25] with ADC ANS[1] and OSC32K_EXTAL of the 32 kHz oscillator (PCR.IBE must be 0). |
| 53 | PB[8] | input | Input-only pad GPIO[24] with ADC ANS[0] and OSC32K_XTAL of the 32 kHz oscillator (PCR.IBE must be 0). |
| 54 | PB[10] | bidirectional | Slow I/O pad with analog feature: GPIO[26], ADC ANS[2] and WKPU[8] wakeup input. |
| 55 | PF[0] | bidirectional | Slow I/O pad with analog feature: GPIO[80], E0UC[10], DSPI_1 CS3_1 and ADC ANS[8]. |
| 56 | PF[1] | bidirectional | Slow I/O pad with analog feature: GPIO[81], E0UC[11], DSPI_1 CS4_1 and ADC ANS[9]. |
| 57 | PF[2] | bidirectional | Slow I/O pad with analog feature: GPIO[82], E0UC[12], DSPI_2 CS0_2 and ADC ANS[10]. |
| 58 | PF[3] | bidirectional | Slow I/O pad with analog feature: GPIO[83], E0UC[13], DSPI_2 CS1_2 and ADC ANS[11]. |
| 59 | PF[4] | bidirectional | Slow I/O pad with analog feature: GPIO[84], E0UC[14], DSPI_2 CS2_2 and ADC ANS[12]. |
| 60 | PF[5] | bidirectional | Slow I/O pad with analog feature: GPIO[85], E0UC[22], DSPI_2 CS3_2 and ADC ANS[13]. |
| 61 | PF[6] | bidirectional | Slow I/O pad with analog feature: GPIO[86], E0UC[23] and ADC ANS[14]. |
| 62 | PF[7] | bidirectional | Slow I/O pad with analog feature: GPIO[87] and ADC ANS[15]. |
| 63 | PD[0] | input | Input-only precise ADC pad GPIO[48] with ADC GPI[4]. |
| 64 | PD[1] | input | Input-only precise ADC pad GPIO[49] with ADC GPI[5]. |
| 65 | PD[2] | input | Input-only precise ADC pad GPIO[50] with ADC GPI[6]. |
| 66 | PD[3] | input | Input-only precise ADC pad GPIO[51] with ADC GPI[7]. |
| 67 | PD[4] | input | Input-only precise ADC pad GPIO[52] with ADC GPI[8]. |
| 68 | PD[5] | input | Input-only precise ADC pad GPIO[53] with ADC GPI[9]. |
| 69 | PD[6] | input | Input-only precise ADC pad GPIO[54] with ADC GPI[10]. |
| 70 | PD[7] | input | Input-only precise ADC pad GPIO[55] with ADC GPI[11]. |
| 71 | PD[8] | input | Input-only precise ADC pad GPIO[56] with ADC GPI[12]. |
| 72 | PB[4] | input | Input-only precise ADC pad GPIO[20] with ADC GPI[0]. |
| 73 | VSS_HV_ADC | power_in | Reference ground and analog ground for the ADC; must be tied to digital VSS externally. |
| 74 | VDD_HV_ADC | power_in | Reference voltage and analog supply for the ADC (3.0-3.6 V or 4.5-5.5 V), within VDD ±0.1 V. |
| 75 | PB[5] | input | Input-only precise ADC pad GPIO[21] with ADC GPI[1]. |
| 76 | PB[6] | input | Input-only precise ADC pad GPIO[22] with ADC GPI[2]. |
| 77 | PB[7] | input | Input-only precise ADC pad GPIO[23] with ADC GPI[3]. |
| 78 | PD[9] | input | Input-only precise ADC pad GPIO[57] with ADC GPI[13]. |
| 79 | PD[10] | input | Input-only precise ADC pad GPIO[58] with ADC GPI[14]. |
| 80 | PD[11] | input | Input-only precise ADC pad GPIO[59] with ADC GPI[15]. |
| 81 | PB[11] | bidirectional | Slow I/O pad with analog feature: GPIO[27], E0UC[3], DSPI_0 CS0_0 and ADC ANS[3]. |
| 82 | PD[12] | bidirectional | Slow I/O pad with analog feature: GPIO[60], DSPI_0 CS5_0, E0UC[24] and ADC ANS[4]. |
| 83 | PB[12] | bidirectional | Slow I/O pad with analog feature: GPIO[28], E0UC[4], DSPI_0 CS1_0 and ADC ANX[0]. |
| 84 | PD[13] | bidirectional | Slow I/O pad with analog feature: GPIO[61], DSPI_1 CS0_1, E0UC[25] and ADC ANS[5]. |
| 85 | PB[13] | bidirectional | Slow I/O pad with analog feature: GPIO[29], E0UC[5], DSPI_0 CS2_0 and ADC ANX[1]. |
| 86 | PD[14] | bidirectional | Slow I/O pad with analog feature: GPIO[62], DSPI_1 CS1_1, E0UC[26] and ADC ANS[6]. |
| 87 | PB[14] | bidirectional | Slow I/O pad with analog feature: GPIO[30], E0UC[6], DSPI_0 CS3_0 and ADC ANX[2]. |
| 88 | PD[15] | bidirectional | Slow I/O pad with analog feature: GPIO[63], DSPI_1 CS2_1, E0UC[27] and ADC ANS[7]. |
| 89 | PB[15] | bidirectional | Slow I/O pad with analog feature: GPIO[31], E0UC[7], DSPI_0 CS4_0 and ADC ANX[3]. |
| 90 | PA[3] | bidirectional | Slow pad GPIO[3] with E0UC[3] and EIRQ[0] input. |
| 91 | PG[13] | bidirectional | Medium pad GPIO[109] with E0UC[27]. |
| 92 | PG[12] | bidirectional | Medium pad GPIO[108] with E0UC[26]. |
| 93 | PH[0] | bidirectional | Medium pad GPIO[112] with E1UC[2] and DSPI_1 SIN1 input. |
| 94 | PH[1] | bidirectional | Medium pad GPIO[113] with E1UC[3] and DSPI_1 SOUT1 output. |
| 95 | PH[2] | bidirectional | Medium pad GPIO[114] with E1UC[4] and DSPI_1 SCK_1. |
| 96 | PH[3] | bidirectional | Medium pad GPIO[115] with E1UC[5] and DSPI_1 CS0_1. |
| 97 | PG[1] | bidirectional | Slow pad GPIO[97] with E1UC[24], CAN5RX input and EIRQ[14] input. |
| 98 | PG[0] | bidirectional | Medium pad GPIO[96] with CAN5TX output and E1UC[23]. |
| 99 | VSS_HV | power_in | Digital ground. |
| 100 | VDD_HV | power_in | Digital supply voltage (3.0-3.6 V or 4.5-5.5 V), with 100 nF between each VDD/VSS pair. |
| 101 | PF[15] | bidirectional | Slow pad GPIO[95] with CAN1RX/CAN4RX inputs and EIRQ[13] input. |
| 102 | PF[14] | bidirectional | Medium pad GPIO[94] with CAN4TX, E1UC[27] and CAN1TX. |
| 103 | PE[13] | bidirectional | Slow pad GPIO[77] with DSPI_2 SOUT2 output and E1UC[20]. |
| 104 | PA[7] | bidirectional | Slow pad GPIO[7] with E0UC[7], LIN3TX output and EIRQ[2] input. |
| 105 | PA[8] | bidirectional | Slow pad GPIO[8] with E0UC[8], EIRQ[3], ABS[0] boot input and LIN3RX; input with weak pull-up at reset. |
| 106 | PA[9] | bidirectional | Slow pad GPIO[9] with E0UC[9] and FAB boot input; pull-down at reset so the device fetches from flash without an external strong pull-up. |
| 107 | PA[10] | bidirectional | Slow pad GPIO[10] with E0UC[10] and I2C_0 SDA. |
| 108 | PA[11] | bidirectional | Slow pad GPIO[11] with E0UC[11] and I2C_0 SCL. |
| 109 | PE[12] | bidirectional | Slow pad GPIO[76] with E1UC[19], DSPI_2 SIN_2 input and EIRQ[11] input. |
| 110 | PG[14] | bidirectional | Slow pad GPIO[110] with E1UC[0]. |
| 111 | PG[15] | bidirectional | Medium pad GPIO[111] with E1UC[1]. |
| 112 | PE[14] | bidirectional | Slow pad GPIO[78] with DSPI_2 SCK_2, E1UC[21] and EIRQ[12] input. |
| 113 | PE[15] | bidirectional | Medium pad GPIO[79] with DSPI_2 CS0_2 and E1UC[22]. |
| 114 | PG[10] | bidirectional | Slow pad GPIO[106] with E0UC[24]. |
| 115 | PG[11] | bidirectional | Medium pad GPIO[107] with E0UC[25]. |
| 116 | PC[3] | bidirectional | Slow pad GPIO[35] with DSPI_1 CS0_1, ADC MA[0], CAN1RX/CAN4RX inputs and EIRQ[6] input. |
| 117 | PC[2] | bidirectional | Medium pad GPIO[34] with DSPI_1 SCK_1, CAN4TX output and EIRQ[5] input. |
| 118 | PA[5] | bidirectional | Medium pad GPIO[5] with E0UC[5]. |
| 119 | PA[6] | bidirectional | Slow pad GPIO[6] with E0UC[6] and EIRQ[1] input. |
| 120 | PH[10] | bidirectional | Slow pad GPIO[122] and JTAG TMS input; input with weak pull-up at reset. |
| 121 | PC[1] | bidirectional | Medium pad GPIO[33] and JTAG TDO output; tristate at reset, external 47-100 kΩ pull-up to VDD_HV recommended on TDO to avoid extra STANDBY current. |
| 122 | VSS_HV | power_in | Digital ground. |
| 123 | VDD_HV | power_in | Digital supply voltage (3.0-3.6 V or 4.5-5.5 V), with 100 nF between each VDD/VSS pair. |
| 124 | VDD_LV | power_in | 1.2 V decoupling pin; a 330 nF capacitor must be connected to the nearest VSS_LV pin. |
| 125 | VSS_LV | power_in | 1.2 V decoupling pin; a 330 nF capacitor must be connected to the nearest VDD_LV pin. |
| 126 | PC[0] | bidirectional | Medium pad GPIO[32] and JTAG TDI input; input with weak pull-up at reset. |
| 127 | PH[9] | bidirectional | Slow pad GPIO[121] and JTAG TCK input; input with weak pull-up at reset. |
| 128 | PE[2] | bidirectional | Medium pad GPIO[66] with E0UC[18] and DSPI_1 SIN_1 input. |
| 129 | PE[3] | bidirectional | Medium pad GPIO[67] with E0UC[19] and DSPI_1 SOUT_1 output. |
| 130 | PC[5] | bidirectional | Medium pad GPIO[37] with DSPI_1 SOUT_1, CAN3TX output and EIRQ[7] input. |
| 131 | PC[4] | bidirectional | Medium pad GPIO[36] with DSPI_1 SIN_1 and CAN3RX inputs. |
| 132 | PE[4] | bidirectional | Medium pad GPIO[68] with E0UC[20], DSPI_1 SCK_1 and EIRQ[9] input. |
| 133 | PE[5] | bidirectional | Medium pad GPIO[69] with E0UC[21], DSPI_1 CS0_1 and ADC MA[2]. |
| 134 | PH[4] | bidirectional | Medium pad GPIO[116] with E1UC[6]. |
| 135 | PH[5] | bidirectional | Slow pad GPIO[117] with E1UC[7]. |
| 136 | PH[6] | bidirectional | Medium pad GPIO[118] with E1UC[8] and ADC MA[2]. |
| 137 | PH[7] | bidirectional | Medium pad GPIO[119] with E1UC[9], DSPI_2 CS3_2 and ADC MA[1]. |
| 138 | PH[8] | bidirectional | Medium pad GPIO[120] with E1UC[10], DSPI_2 CS2_2 and ADC MA[0]. |
| 139 | PE[6] | bidirectional | Medium pad GPIO[70] with E0UC[22], DSPI_0 CS3_0 and ADC MA[1]. |
| 140 | PE[7] | bidirectional | Medium pad GPIO[71] with E0UC[23], DSPI_0 CS2_0 and ADC MA[0]. |
| 141 | PC[12] | bidirectional | Medium pad GPIO[44] with E0UC[12] and DSPI_2 SIN_2 input. |
| 142 | PC[13] | bidirectional | Slow pad GPIO[45] with E0UC[13] and DSPI_2 SOUT_2 output. |
| 143 | PC[8] | bidirectional | Slow pad GPIO[40] with LIN2TX output. |
| 144 | PB[2] | bidirectional | Medium pad GPIO[18] with LIN0TX output and I2C_0 SDA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-144(20x20) |
| Category | Embedded Processors & Controllers |
| Pins | 144 |

## CAD (KiCad official)

- Symbol: `SPC560B50L5C6E0Y`
- Footprint: `Package_QFP:LQFP-144_20x20mm_P0.5mm`
- 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
- 3D model files: `spc560b50l5c6e0y-etched.step` / `spc560b50l5c6e0y-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `spc560b50l5c6e0y.step` / `spc560b50l5c6e0y.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8563121962953031680) (116 pp, sha256 `17b37543a9b5ee31`, retrieved 2026-09-29, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/spc560b50l5c6e0y-datasheet.pdf)