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Contents

README

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SP8810DTS

Siliup · MOSFETs · SOT-23-6L

SP8810DTS from Siliup, in a SOT-23-6L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of MOSFET 1 (N-channel, 20V VDSS, 7A continuous drain current per device rating).
2 D1,2 passive Common drain of MOSFET 1 and MOSFET 2, internally tied to pin 5 (20V VDSS, 7A ID).
3 S2 passive Source of MOSFET 2 (N-channel, 20V VDSS, 7A continuous drain current per device rating).
4 G2 input Gate of MOSFET 2, ESD protected to 2KV, with gate-source voltage limited to ±12V and threshold 0.4 to 1.0V.
5 D1,2 passive Common drain of MOSFET 1 and MOSFET 2, internally tied to pin 2 (20V VDSS, 7A ID).
6 G1 input Gate of MOSFET 1, ESD protected to 2KV, with gate-source voltage limited to ±12V and threshold 0.4 to 1.0V.

Key specifications

Parameter Value
Manufacturer Siliup
Package SOT-23-6L
Category Transistors/Thyristors
Pins 6

CAD (KiCad official)

  • Symbol: SP8810DTS
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6L (KiCad packages3D, STEP)
  • 3D model files: sp8810dts-etched.step / sp8810dts-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sp8810dts.step / sp8810dts.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Siliup datasheet (5 pp, sha256 791bbd3e85ced9f0, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF