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SP706REN-L-TP
Public Made by Adomby adom
TECH PUBLIC Supervisor And Reset ICs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SP706REN-L-TP
TECH PUBLIC · Supervisor And Reset ICs · SOP-8
SP706REN-L-TP from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Active-low manual-reset input that triggers a reset pulse when pulled below 0.8V, with an internal 250µA pull-up current. |
| 2 | VCC | power_in | Supply input. |
| 3 | GND | power_in | Ground reference for all signals. |
| 4 | PFI | input | Power-fail voltage monitor input; PFO goes low when PFI is below 1.25V, and PFI should be connected to GND or VCC when not used. |
| 5 | PFO | output | Power-fail output that goes low and sinks current when PFI is less than 1.25V, otherwise stays high. |
| 6 | WDI | input | Watchdog input; if it stays high or low for 1.6s WDO goes low, and floating it or connecting it to a high-impedance three-state buffer disables the watchdog. |
| 7 | RESET | output | Active-low reset output that pulses low for 200ms when triggered and stays low whenever VCC is below the reset threshold, remaining low 200ms after VCC rises above the threshold or MR goes high. |
| 8 | WDO | output | Watchdog output that pulls low when the 1.6s internal watchdog timer finishes counting and stays low until the watchdog is cleared, and also goes low when VCC is below the reset threshold. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
SP706REN-L-TP - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
sp706ren-l-tp-etched.step/sp706ren-l-tp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sp706ren-l-tp.step/sp706ren-l-tp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TECH PUBLIC datasheet (7 pp, sha256
8feb945e86943364, retrieved 2026-11-05, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SP706REN-L-TP
**TECH PUBLIC** · Supervisor And Reset ICs · SOP-8
SP706REN-L-TP from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Active-low manual-reset input that triggers a reset pulse when pulled below 0.8V, with an internal 250µA pull-up current. |
| 2 | VCC | power_in | Supply input. |
| 3 | GND | power_in | Ground reference for all signals. |
| 4 | PFI | input | Power-fail voltage monitor input; PFO goes low when PFI is below 1.25V, and PFI should be connected to GND or VCC when not used. |
| 5 | PFO | output | Power-fail output that goes low and sinks current when PFI is less than 1.25V, otherwise stays high. |
| 6 | WDI | input | Watchdog input; if it stays high or low for 1.6s WDO goes low, and floating it or connecting it to a high-impedance three-state buffer disables the watchdog. |
| 7 | RESET | output | Active-low reset output that pulses low for 200ms when triggered and stays low whenever VCC is below the reset threshold, remaining low 200ms after VCC rises above the threshold or MR goes high. |
| 8 | WDO | output | Watchdog output that pulls low when the 1.6s internal watchdog timer finishes counting and stays low until the watchdog is cleared, and also goes low when VCC is below the reset threshold. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `SP706REN-L-TP`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `sp706ren-l-tp-etched.step` / `sp706ren-l-tp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sp706ren-l-tp.step` / `sp706ren-l-tp.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TECH PUBLIC datasheet](docs/sp706ren-l-tp-datasheet.pdf) (7 pp, sha256 `8feb945e86943364`, retrieved 2026-11-05, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sp706ren-l-tp-datasheet.pdf)