component
SP490ECN-L
Public Made by Adomby adom
MaxLinear Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSP490ECN-L
MaxLinear · Pre-ordered Chips · SOIC-8
SP490ECN-L from MaxLinear, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Positive supply, specified at 4.75 V to 5.25 V (5 V ±5%). |
| 2 | R | output | Receiver output, which is held high by the fail-safe feature when the receiver inputs are left unconnected. |
| 3 | D | input | Driver input, with logic-high minimum of 2.0 V and logic-low maximum of 0.8 V. |
| 4 | GND | power_in | Ground connection. |
| 5 | Y | output | Non-inverting driver output, which swings about 0 V to +5 V unloaded and maintains greater than 1.5 V differential with a 54 Ω worst-case load. |
| 6 | Z | output | Inverting driver output, forming the complementary half of the differential RS-485/RS-422 output pair with Y. |
| 7 | B | input | Inverting receiver input, with input resistance of 12 kΩ minimum and 15 kΩ typical over a -7 V to 12 V common-mode range. |
| 8 | A | input | Non-inverting receiver input, with differential input sensitivity as low as ±200 mV over a -7 V to 12 V common-mode range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MaxLinear |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | 7 | V | 2 | |||
| Driver input voltage | -0.5 | V | Upper limit printed as VCC + 0.5V | 2 | |||
| Receiver input voltage | -14 | 14 | V | 2 | |||
| Driver output voltage | -14 | 14 | V | 2 | |||
| Receiver output voltage | -0.5 | V | Upper limit printed as VCC + 0.5V | 2 | |||
| Storage temperature | -65 | 150 | °C | 2 | |||
| Supply voltage | VCC | 4.75 | 5.25 | V | 3 | ||
| Operating temperature, commercial (C) | TAMB | 0 | 70 | °C | 3 | ||
| Differential output voltage, RS-422 load | 2 | V | With load; R = 50Ω (RS-422); Figure 1 | 2 | |||
| Differential output voltage, RS-485 load | 1.5 | V | With load; R = 27Ω (RS-485); Figure 1 | 2 | |||
| Change in magnitude of driver differential output voltage for complementary states | 0.2 | V | R = 27Ω or R = 50Ω; Figure 1 | 2 | |||
| Driver common-mode output voltage | 3 | V | R = 27Ω or R = 50Ω; Figure 1 | 2 | |||
| Input high voltage | VIH | 2 | V | Applies to D | 2 | ||
| Input low voltage | VIL | 0.8 | V | Applies to D | 2 | ||
| Input current | -10 | 10 | µA | Applies to D | 2 | ||
| Driver short circuit current, VOUT = HIGH | -250 | 250 | mA | -7V ≤ VO ≤ 12V | 2 | ||
| Driver short circuit current, VOUT = LOW | -250 | 250 | mA | -7V ≤ VO ≤ 12V | 2 | ||
| Maximum data rate (driver) | 10 | Mbps | 2 | ||||
| Driver input to output, tPLH | tPLH | 30 | 60 | ns | RDIFF = 54Ω, CL1 = CL2 = 100pF; Figures 3 & 5 | 2 | |
| Driver input to output, tPHL | tPHL | 30 | 60 | ns | RDIFF = 54Ω, CL1 = CL2 = 100pF; Figures 3 & 5 | 2 | |
| Driver skew | tSKEW | 5 | ns | tSKEW = /tDPLH - tDPHL/; Figures 3 & 5 | 2 | ||
| Driver rise or fall time | 15 | 40 | ns | From 10%-90%; RDIFF = 54Ω, CL1 = CL2 = 100pF; Figures 3 & 5 | 2 | ||
| Differential input threshold | VTH | -0.2 | 0.2 | V | -7V ≤ VCM ≤ 12V | 3 | |
| Input hysteresis | 70 | mV | VCM = 0V | 3 | |||
| Output voltage HIGH | VOH | 3.5 | V | VID = 200mV, IO = -4mA | 3 | ||
| Output voltage LOW | VOL | 0.4 | V | VID = -200mV, IO = 4mA | 3 | ||
| Input resistance | RIN | 12 | 15 | kΩ | -7V ≤ VCM ≤ 12V | 3 | |
| Input current (A, B) at VIN = 12V | IIN | -1 | 1 | mA | VIN = 12V | 3 | |
| Input current (A, B) at VIN = -7V | IIN | -0.8 | mA | VIN = -7V | 3 | ||
| Receiver short circuit current | IOS | 85 | mA | 0V ≤ VO ≤ VCC | 3 | ||
| Maximum data rate (receiver) | 10 | Mbps | 3 | ||||
| Receiver input to output, tPLH | tPLH | 20 | 45 | 100 | ns | RDIFF = 54Ω, CL1 = CL2 = 100pF; Figures 3 and 7 | 3 |
| Receiver input to output, tPHL | tPHL | 20 | 45 | 100 | ns | RDIFF = 54Ω, CL1 = CL2 = 100pF; Figures 3 and 7 | 3 |
| Differential receiver skew | /tPLH - tPHL/ | 13 | ns | RDIFF = 54Ω, CL1 = CL2 = 100pF; Figures 3 and 7 | 3 | ||
| Supply current | ICC | 900 | µA | 3 |
CAD (KiCad official)
- Symbol:
SP490ECN-L - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
sp490ecn-l-etched.step/sp490ecn-l-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sp490ecn-l.step/sp490ecn-l.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MaxLinear datasheet (13 pp, sha256
6384730ddfde24eb, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).