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SP3072EMN-L

Public Made by Adom

by adom

MaxLinear Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SP3072EMN-L

MaxLinear · Pre-ordered Chips · SOIC-8

SP3072EMN-L from MaxLinear, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RO output Receiver Output: when RE is low, RO is high if (A-B) ≥ -50mV and low if (A-B) ≤ -200mV.
2 RE input Receiver Output Enable: low enables RO, high makes RO high impedance; RE high with DE low enters shutdown, and RE is a hot-swap input.
3 DE input Driver Output Enable: high enables the driver outputs, low makes them high impedance; DE low with RE high enters shutdown, and DE is a hot-swap input.
4 DI input Driver Input: with DE high, a low on DI forces the noninverting output low and inverting output high, and a high on DI does the opposite.
5 GND power_in Ground.
6 A bidirectional Noninverting Receiver Input and Noninverting Driver Output.
7 B bidirectional Inverting Receiver Input and Inverting Driver Output.
8 VCC power_in Positive supply (3.3V operation); bypass VCC to GND with a 0.1µF capacitor.

Key specifications

Parameter Value
Manufacturer MaxLinear
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Differential driver output VOD 2 V RL = 100 (RS-422), Figure 5 9
Differential driver output VOD 1.5 V RL = 54 (RS-485), Figure 5 9
Change in magnitude of differential output voltage ΔVOD 0.2 V RL = 54 or 100, Figure 5 9
Driver common mode output voltage VOC 3 V RL = 54 or 100, Figure 5 9
Change in magnitude of common mode output voltage Δ/VOC/ -0.2 0.2 V RL = 54 or 100, Figure 5 9
Input high voltage VIH 2 V DE, DI, RE 9
Input low voltage VIL 0.8 V DE, DI, RE 9
Input hysteresis VHYS 100 mV DE, DI, RE 9
Input current IIN -1 1 µA DE, DI, RE 9
Output leakage (Y and Z) IO 125 µA DE = GND, VCC = GND or 3.6V, VIN = 12V 9
Output leakage (Y and Z) IO -100 µA DE = GND, VCC = GND or 3.6V, VIN = -7V 9
Input current (A and B) half duplex IA,B 125 µA DE = GND, VCC = GND or 3.6V, VIN = 12V 9
Input current (A and B) half duplex IA,B -100 µA DE = GND, VCC = GND or 3.6V, VIN = -7V 9
Thermal-shutdown threshold TTS 165 °C 9
Thermal-shutdown hysteresis TTSH 15 °C 9
Receiver differential threshold (sensitivity) VTH -200 -125 -50 mV -7V ≤ VCM ≤ 12V 9
Receiver input hysteresis VTH 15 mV Va + Vb = 0V 9
RO output low voltage VOL 0.4 V IO = 1mA 9
Tri-State output current at receiver IOZR -1 1 µA 0 ≤ VO ≤ VCC 9
Receiver input resistance RIN 96 kΩ -7V ≤ VCM ≤ 12V 9
Supply current ICC 0.8 1.5 mA No load, RE = GND, DE = VCC 10
Supply current in shutdown mode ISHDN 0.05 3 µA RE = VCC, DE = GND 10
Driver propagation delay tPHL, tPLH 250 1500 ns RL = 54Ω, CL = 50pF, Figure 7 11
Driver output rise / fall time tR, tF 350 1600 ns RL = 54Ω, CL = 50pF, Figure 7 11
Driver differential skew tPLH - tPHL 200 ns RL = 54Ω, CL = 50pF, Figure 7 11
Driver enable to output high tZH 2500 ns RL = 500Ω, CL = 50pF, Figure 8 & Figure 10 11
Driver enable to output low tZL 2500 ns RL = 500Ω, CL = 50pF, Figure 8 & Figure 10 11
Driver disable from output high tHZ 100 ns RL = 500Ω, CL = 50pF, Figure 8 & Figure 10 11
Driver disable from output low tLZ 100 ns RL = 500Ω, CL = 50pF, Figure 8 & Figure 10 11
Driver enable from shutdown to output high tZH(SHDN) 5500 ns Figure 8 11
Driver enable from shutdown to output low tZL(SHDN) 5500 ns Figure 10 11
Driver time to shutdown tSHDN 50 200 600 ns 11
Receiver propagation delay tPHL, tPLH 200 ns CL = 15pF, Figure 11 11
Receiver propagation delay skew tPLH - tPHL 30 ns CL = 15pF, Figure 11 11
Receiver enable to output high tZH 50 ns Figure 12 & Figure 13 11
Receiver enable to output low tZL 50 ns Figure 12 & Figure 13 11
Receiver disable from output high tHZ 100 ns Figure 12 & Figure 13 11
Receiver disable from output low tLZ 200 ns Figure 12 & Figure 13 11
Receiver enable from shutdown to output high 4000 ns Figure 12 & Figure 13 11
Receiver enable from shutdown to output low 4000 ns Figure 12 & Figure 13 11
Receiver time to shutdown tSHDN 50 200 600 ns 11
Supply voltage VCC 6 V 8
Input voltage at control input pins (RE, DE) -0.3 6 V 8
Driver input voltage (RE, DE) -0.3 6 V 8
Driver output voltage (A, B, Y & Z) -8 13 V 8
Receiver input voltage (A, B) -8 13 V 8
Receiver output current -60 60 mA 8
Continuous power dissipation 471 mW TA = 70°C, 8-pin NSOIC (derate 5.88mW/°C above 70°C) 8
Operating temperature range (SP307xE_MN) -40 125 °C 8
Junction temperature 150 °C 8
Storage temperature range -65 150 °C 8
Lead temperature (soldering, 10s) 300 °C 8
HBM ESD (pins Y, Z, A & B) -15 15 kV Human Body Model 8

CAD (KiCad official)

  • Symbol: SP3072EMN-L
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sp3072emn-l-etched.step / sp3072emn-l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sp3072emn-l.step / sp3072emn-l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MaxLinear datasheet (26 pp, sha256 1c86e00ee7864120, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF