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SP3022CP8

Siliup · MOSFETs · SOP-8

SP3022CP8 from Siliup, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of MOSFET 1 (shown as the N-channel device, 30V, 7A, RDS(on) typ 18mΩ at VGS=10V).
2 G1 input Gate of MOSFET 1 (N-channel); VGS maximum ±20V, threshold 1V min to 2.5V max at 250uA.
3 S2 passive Source of MOSFET 2 (shown as the P-channel device, -30V, -8A, RDS(on) typ 19mΩ at VGS=-10V).
4 G2 input Gate of MOSFET 2 (P-channel); VGS maximum ±20V, threshold -1V min to -2.5V max at -250uA.
5 D2 passive Drain of MOSFET 2 (P-channel), tied to pin 6; VDS rated -30V, continuous ID -8A.
6 D2 passive Drain of MOSFET 2 (P-channel), tied to pin 5; pulsed drain current IDM -32A.
7 D1 passive Drain of MOSFET 1 (N-channel), tied to pin 8; VDS rated 30V, continuous ID 7A.
8 D1 passive Drain of MOSFET 1 (N-channel), tied to pin 7; pulsed drain current IDM 28A.

Key specifications

Parameter Value
Manufacturer Siliup
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: SP3022CP8
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: sp3022cp8-etched.step / sp3022cp8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sp3022cp8.step / sp3022cp8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Siliup datasheet (8 pp, sha256 0027bd260a4f53ea, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF