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Contents

README

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SP2004KT7

Siliup · MOSFETs · SOT-723

SP2004KT7 from Siliup, in a SOT-723. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate; gate-source voltage limited to ±12 V, with a gate threshold of -0.35 to -1.00 V and ESD protection to 2KV.
2 S passive Source of the P-channel MOSFET; continuous drain current is -0.7 A (pulsed -2.8 A) and drain-source voltage is -20 V.
3 D passive Drain of the P-channel MOSFET; VDSS is -20 V, continuous ID is -0.7 A, and RDS(on) is 400 mΩ typ at VGS=-4.5 V.

Key specifications

Parameter Value
Manufacturer Siliup
Package SOT-723
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: SP2004KT7
  • Footprint: Package_TO_SOT_SMD:SOT-723
  • 3D model: SOT-723, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.5 mm nominal SOT-723 height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: sp2004kt7-etched.step / sp2004kt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sp2004kt7.step / sp2004kt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Siliup datasheet (5 pp, sha256 e835450d36d9ffee, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF