component
SP1001-04JTG
Public Made by Adomby adom
Littelfuse ESD And Surge Protection (TVS/ESD), SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSP1001-04JTG
Littelfuse · ESD And Surge Protection (TVS/ESD) · SC-70-5
SP1001-04JTG from Littelfuse, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | ESD-protected I/O channel (steering diode pair to the common rail), 8pF typ capacitance, ±15kV contact ESD per IEC 61000-4-2. |
| 2 | GND | power_in | Common ground/Zener return pin, tied to shield or signal ground in the application example. |
| 3 | I/O2 | passive | ESD-protected I/O channel (steering diode pair to the common rail), 8pF typ capacitance, ±15kV contact ESD per IEC 61000-4-2. |
| 4 | I/O3 | passive | ESD-protected I/O channel (steering diode pair to the common rail), 8pF typ capacitance, ±15kV contact ESD per IEC 61000-4-2. |
| 5 | I/O4 | passive | ESD-protected I/O channel (steering diode pair to the common rail), 8pF typ capacitance, ±15kV contact ESD per IEC 61000-4-2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Littelfuse |
| Package | SC-70-5 |
| Category | Circuit Protection |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Peak Current (tp=8/20μs) | IPP | 2 | A | tp=8/20μs | 2 | ||
| Operating Temperature | TOP | -40 | 125 | °C | 2 | ||
| Storage Temperature | TSTOR | -55 | 150 | °C | 2 | ||
| Forward Voltage Drop | VF | 0.7 | 0.9 | 1.2 | V | IF=10mA | 2 |
| Reverse Voltage Drop | VR | 6 | 8.5 | V | IR=1mA | 2 | |
| Reverse Standoff Voltage | VRWM | 5.5 | V | IR≤1µA | 2 | ||
| Reverse Leakage Current | ILEAK | 0.1 | µA | VR=5V | 2 | ||
| Clamp Voltage | VC | 8 | 11 | V | IPP=1A, tp=8/20µs, Fwd | 2 | |
| Clamp Voltage | VC | 9.7 | 13 | V | IPP=2A, tp=8/20µs, Fwd | 2 | |
| ESD Withstand Voltage (contact) | VESD | -15 | 15 | kV | IEC61000-4-2 (Contact) | 2 | |
| ESD Withstand Voltage (air) | VESD | -30 | 30 | kV | IEC61000-4-2 (Air) | 2 | |
| Maximum Junction Temperature | 150 | °C | 2 | ||||
| Maximum Lead Temperature (Soldering) | 260 | °C | Soldering 20s-40s | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Lead Plating Matte Tin (SC70-x) Pre-Plated Frame (SOT5x3, SOT963) | 3 |
CAD (KiCad official)
- Symbol:
SP1001-04JTG - Footprint:
Package_TO_SOT_SMD:SOT-353_SC-70-5 - 3D model: SC-70-5 (KiCad packages3D, STEP)
- 3D model files:
sp1001-04jtg-etched.step/sp1001-04jtg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sp1001-04jtg.step/sp1001-04jtg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Littelfuse datasheet (7 pp, sha256
009191d4f8096725, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).