# SN75LVDS32DR

**Texas Instruments** · LVDS ICs · SOIC-16

SN75LVDS32DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1B | input | Inverting differential input of receiver 1, which with 1A forms an LVDS pair with differential input thresholds of ±100 mV max and a recommended |VID| of 0.1 V to 0.6 V. |
| 2 | 1A | input | Non-inverting differential input of receiver 1; Y goes high when VID (A minus B) is 100 mV or more, with thresholds of ±100 mV max and recommended |VID| of 0.1 V to 0.6 V. |
| 3 | 1Y | tri_state | LVTTL output of receiver 1, high for VID ≥ 100 mV or an open input, and high impedance when the enables are inactive. |
| 4 | G | input | Active-high enable shared by receivers 1 and 2; outputs are enabled when G is high and the complementary enable is low, with VIH of 2 V min and VIL of 0.8 V max. |
| 5 | 2Y | tri_state | LVTTL output of receiver 2, high for VID ≥ 100 mV or an open input, and high impedance when the enables are inactive. |
| 6 | 2A | input | Non-inverting differential input of receiver 2, with thresholds of ±100 mV max and recommended |VID| of 0.1 V to 0.6 V. |
| 7 | 2B | input | Inverting differential input of receiver 2, with thresholds of ±100 mV max and recommended |VID| of 0.1 V to 0.6 V. |
| 8 | GND | power_in | Ground reference for the device; input common-mode range allows 1 V of ground potential difference between LVDS nodes. |
| 9 | 3B | input | Inverting differential input of receiver 3, with thresholds of ±100 mV max and recommended |VID| of 0.1 V to 0.6 V. |
| 10 | 3A | input | Non-inverting differential input of receiver 3, with thresholds of ±100 mV max and recommended |VID| of 0.1 V to 0.6 V. |
| 11 | 3Y | tri_state | LVTTL output of receiver 3, high for VID ≥ 100 mV or an open input, and high impedance when the enables are inactive. |
| 12 | ~{G} | input | Active-low enable shared by receivers 3 and 4; outputs are enabled when this pin is low and G is high, with VIH of 2 V min and VIL of 0.8 V max. |
| 13 | 4Y | tri_state | LVTTL output of receiver 4, high for VID ≥ 100 mV or an open input, and high impedance when the enables are inactive. |
| 14 | 4A | input | Non-inverting differential input of receiver 4, with thresholds of ±100 mV max and recommended |VID| of 0.1 V to 0.6 V. |
| 15 | 4B | input | Inverting differential input of receiver 4, with thresholds of ±100 mV max and recommended |VID| of 0.1 V to 0.6 V. |
| 16 | VCC | power_in | Single supply, 3 V to 3.6 V (3.3 V nominal) per recommended operating conditions. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Interface |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `SN75LVDS32DR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `sn75lvds32dr-etched.step` / `sn75lvds32dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn75lvds32dr.step` / `sn75lvds32dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn75lvds32.pdf) (20 pp, sha256 `694012f3d1ab2df9`, retrieved 2026-10-11, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn75lvds32dr-datasheet.pdf)