component
SN75LVCP601RTJR
Public Made by Adomby adom
Texas Instruments Signal Buffers, Repeaters, Splitters, QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"description": "Texas Instruments Signal Buffers, Repeaters, Splitters, QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"component": {
"mpn": "SN75LVCP601RTJR",
"manufacturer": "Texas Instruments",
"package": "QFN-20-EP(4x4)",
"pin_count": 21,
"category": "Communication Interface Chip/UART/485/232",
"subcategory": "Signal Buffers, Repeaters, Splitters",
"datasheet": "https://www.ti.com/cn/lit/gpn/sn75lvcp601",
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"distributor_links": {
"lcsc": "C544765",
"digikey": "296-41655-2-ND",
"mouser": "595-SN75LVCP601RTJR"
},
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"pins": [
{
"number": "1",
"name": "RX1P",
"type": "input",
"description": "Noninverting CML differential input for CH1, connected to an internal voltage bias via a dual-termination resistor circuit."
},
{
"number": "2",
"name": "RX1N",
"type": "input",
"description": "Inverting CML differential input for CH1, connected to an internal voltage bias via a dual-termination resistor circuit."
},
{
"number": "3",
"name": "GND",
"type": "power_in",
"description": "Power supply ground."
},
{
"number": "4",
"name": "TX2N",
"type": "output",
"description": "Inverting VML differential output for CH2, connected internally to voltage bias via termination resistors."
},
{
"number": "5",
"name": "TX2P",
"type": "output",
"description": "Noninverting VML differential output for CH2, connected internally to voltage bias via termination resistors."
},
{
"number": "6",
"name": "DEW2",
"type": "input",
"description": "LVCMOS de-emphasis width control: 0 = short pulse duration, 1 = long pulse duration (default)."
},
{
"number": "7",
"name": "EN",
"type": "input",
"description": "LVCMOS device enable, internally pulled to VCC: 0 = standby mode, 1 = device enabled (default)."
},
{
"number": "8",
"name": "DE2",
"type": "input",
"description": "LVCMOS 3-state input that selects de-emphasis settings per Table 1, internally tied to VCC/2 (>200-kΩ pullup or pulldown)."
},
{
"number": "9",
"name": "DE1",
"type": "input",
"description": "LVCMOS 3-state input that selects de-emphasis settings per Table 1, internally tied to VCC/2 (>200-kΩ pullup or pulldown)."
},
{
"number": "10",
"name": "VCC",
"type": "power_in",
"description": "Positive supply, must be 3.3 V ± 10%."
},
{
"number": "11",
"name": "RX2P",
"type": "input",
"description": "Noninverting CML differential input for CH2, connected to an internal voltage bias via a dual-termination resistor circuit."
},
{
"number": "12",
"name": "RX2N",
"type": "input",
"description": "Inverting CML differential input for CH2, connected to an internal voltage bias via a dual-termination resistor circuit."
},
{
"number": "13",
"name": "GND",
"type": "power_in",
"description": "Power supply ground."
},
{
"number": "14",
"name": "TX1N",
"type": "output",
"description": "Inverting VML differential output for CH1, connected internally to voltage bias via termination resistors."
},
{
"number": "15",
"name": "TX1P",
"type": "output",
"description": "Noninverting VML differential output for CH1, connected internally to voltage bias via termination resistors."
},
{
"number": "16",
"name": "DEW1",
"type": "input",
"description": "LVCMOS de-emphasis width control: 0 = short pulse duration, 1 = long pulse duration (default)."
},
{
"number": "17",
"name": "EQ1",
"type": "input",
"description": "LVCMOS 3-state input that selects equalization settings per Table 1, internally tied to VCC/2 (>200-kΩ pullup or pulldown)."
},
{
"number": "18",
"name": "GND",
"type": "power_in",
"description": "Power supply ground."
},
{
"number": "19",
"name": "EQ2",
"type": "input",
"description": "LVCMOS 3-state input that selects equalization settings per Table 1, internally tied to VCC/2 (>200-kΩ pullup or pulldown)."
},
{
"number": "20",
"name": "VCC",
"type": "power_in",
"description": "Positive supply, must be 3.3 V ± 10%."
},
{
"number": "21",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-sonnet-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pin Configuration heading on page 4 says '16-Pin WQFN' but the pin table, thermal table and orderabl; Thermal pad has no printed pin number; the figure says it must be soldered to the PCB GND plane. It ; The page 4 table text is garbled for DEW1/DEW2 and DE1/DE2 or EQ1/EQ2 (shared descriptions). Pin num"
],
"pages_sent": 8,
"cost_usd": 0.1096,
"at": "2026-10-27T00:39:50"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/sn75lvcp601",
"pages": 35,
"sha256": "5a7c2e15ad114f17",
"source_tier": "lcsc"
},
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"pins": {
"total": 21,
"described": 21,
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"refuses_to_fabricate": true
}
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