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SN75LVCP601RTJR

Public Made by Adom

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Texas Instruments Signal Buffers, Repeaters, Splitters, QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN75LVCP601RTJR

Texas Instruments · Signal Buffers, Repeaters, Splitters · QFN-20-EP(4x4)

SN75LVCP601RTJR from Texas Instruments, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RX1P input Noninverting CML differential input for CH1, connected to an internal voltage bias via a dual-termination resistor circuit.
2 RX1N input Inverting CML differential input for CH1, connected to an internal voltage bias via a dual-termination resistor circuit.
3 GND power_in Power supply ground.
4 TX2N output Inverting VML differential output for CH2, connected internally to voltage bias via termination resistors.
5 TX2P output Noninverting VML differential output for CH2, connected internally to voltage bias via termination resistors.
6 DEW2 input LVCMOS de-emphasis width control: 0 = short pulse duration, 1 = long pulse duration (default).
7 EN input LVCMOS device enable, internally pulled to VCC: 0 = standby mode, 1 = device enabled (default).
8 DE2 input LVCMOS 3-state input that selects de-emphasis settings per Table 1, internally tied to VCC/2 (>200-kΩ pullup or pulldown).
9 DE1 input LVCMOS 3-state input that selects de-emphasis settings per Table 1, internally tied to VCC/2 (>200-kΩ pullup or pulldown).
10 VCC power_in Positive supply, must be 3.3 V ± 10%.
11 RX2P input Noninverting CML differential input for CH2, connected to an internal voltage bias via a dual-termination resistor circuit.
12 RX2N input Inverting CML differential input for CH2, connected to an internal voltage bias via a dual-termination resistor circuit.
13 GND power_in Power supply ground.
14 TX1N output Inverting VML differential output for CH1, connected internally to voltage bias via termination resistors.
15 TX1P output Noninverting VML differential output for CH1, connected internally to voltage bias via termination resistors.
16 DEW1 input LVCMOS de-emphasis width control: 0 = short pulse duration, 1 = long pulse duration (default).
17 EQ1 input LVCMOS 3-state input that selects equalization settings per Table 1, internally tied to VCC/2 (>200-kΩ pullup or pulldown).
18 GND power_in Power supply ground.
19 EQ2 input LVCMOS 3-state input that selects equalization settings per Table 1, internally tied to VCC/2 (>200-kΩ pullup or pulldown).
20 VCC power_in Positive supply, must be 3.3 V ± 10%.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-20-EP(4x4)
Category Communication Interface Chip/UART/485/232
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 4 V 5
Differential I/O voltage range -0.5 4 V 5
Storage temperature Tstg 150 °C 5
ESD HBM V(ESD) -10000 10000 V Human body model per ANSI/ESDA/JEDEC JS-001 5
ESD CDM V(ESD) -1500 1500 V Charged-device model per JESD22-C101 5
ESD Machine model V(ESD) -200 200 V Machine model 5
Supply voltage VCC 3 3.3 3.6 V 5
Coupling capacitor CCOUPLING 12 nF 5
Operating free-air temperature TA 0 85 °C 5
Junction-to-ambient thermal resistance RθJA 38 °C/W RTJ (WQFN) 20 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 40 °C/W 5
Junction-to-board thermal resistance RθJB 10 °C/W 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 15.2 °C/W 5
Power dissipation in active mode PD 215 288 mW DEWx = EN = VCC, EQx = DEx = NC, K28.5 pattern at 6 Gbps, VID = 700 mVp-p 6
Power dissipation in standby mode PSD 5 mW EN = 0 V, DEWx = EQx = DEx = NC, K28.5 pattern at 6 Gbps, VID = 700 mVp-p 6
Active-mode supply current ICC 65 80 mA EN = 3.3 V, DEWx = 0 V, EQx = DEx = NC, K28.5 pattern at 6 Gbps, VID = 700 mVp-p 6
Active power-save mode ICC ICC_ALP 6.5 10 mA When device is enabled and auto low-power conditions are met 6
Standby mode supply current ICC_STDBY 1 mA EN = 0 V 6
Data rate 1 6 Gbps Maximum data rate 6
Input OOB threshold VOOB 50 78 150 mVpp f = 750 MHz 6
OOB differential delta DVdiffOOB 25 mV 6
OOB common-mode delta DVCMOOB 50 mV 6
Input high voltage VIH 1.4 V For all control pins 6
Input low voltage VIL 0.5 V For all control pins 6
Input hysteresis VINHYS 115 mV 6
High-level input current (EQx, DEx) IIH 30 µA EQx, DEx = VCC 6
High-level input current (EN, DEWx) IIH 1 µA EN, DEWx = VCC 6
Low-level input current (EQx, DEx) IIL -30 µA EQx, DEx = GND 6
Low-level input current (EN, DEWx) IIL -10 µA EN, DEWx = GND 6
Receiver differential-input impedance ZDIFFRX 85 100 115 Ω 6
Receiver single-ended input impedance ZSERX 40 Ω 6
Receiver common-mode voltage VCMRX 1.8 V 6
Differential input voltage PP VdiffRX 120 1600 mVppd f = 1.5 GHz and 3 GHz 6
Transmitter pair differential impedance ZdiffTX 85 100 122 Ω 7
Transmitter single-ended impedance ZSETX 40 Ω 7
Sequencing transient voltage VTXtrans -1.2 1.2 V Transient voltages on the serial data bus during power sequencing (lab load) 7
Output de-emphasis, DE = 1 DE -2 dB f = 3 GHz, DE1 or DE2 = 1 7
Output de-emphasis, DE = NC DE -4 dB f = 3 GHz, DE1 or DE2 = NC 7
Differential output swing dc level, DE = 0 DiffVppTX_DE 550 mV f = 3 GHz, DE1 or DE2 = 0 7
Differential output swing dc level, DE = 1 DiffVppTX_DE 830 mV f = 3 GHz, DE1 or DE2 = 1 7
Differential output swing dc level, DE = NC DiffVppTX_DE 630 mV f = 3 GHz, DE1or DE2 = NC 7
Transmitter common-mode voltage VCMTX 1.8 V 7
TX rise-fall imbalance TxR/FImb 6 20 % At 3 Gbps 7
TX amplitude imbalance TxAmpImb 2 10 % 7
Auto low-power entry time AutoLPENTRY 80 105 130 µs Electrical idle at input (see Figure 4) 8
Auto low-power exit time AutoLPEXIT 42 50 ns After first signal activity (see Figure 4) 8
De-emphasis duration, DEW = 0 tDE 94 ps DEW1 or DEW2 = 0 8
De-emphasis duration, DEW = 1 tDE 215 ps DEW1 or DEW2 = 1 8
OOB mode enter tOOB1 3 5 ns See Figure 4 8
OOB mode exit tOOB2 3 5 ns See Figure 4 8
Propagation delay tPDelay 323 400 ps Measured using K28.5 pattern (see Figure 2) 8
Device enable time tENB 5 µs EN 0 → 1 8
Device disable time tDIS 2 µs EN 1 → 0 8
Receiver rise/fall time t20-80RX 62 75 ps 20% to 80%, SATA 6-Gbps, measured 1 in (2.5 cm) from device pin 8
Receiver differential skew tskewRX 30 ps 8
Transmitter rise/fall time t20-80TX 42 55 75 ps 20% to 80%, at 6 Gbps under no load conditions 8
Transmitter differential skew tskewTX 6 20 ps 8
Deterministic jitter DJTX 0.06 0.07 UIp-p VID = 500 mVpp, UI = 333 ps, K28.5 control character 8
Residual random jitter RJTX 0.01 2 ps-rms VID = 500 mVpp, UI = 333 ps, K28.7 control character 8
Deterministic jitter DJTX 0.08 0.16 UIp-p VID = 500 mVpp, UI = 167 ps, K28.5 control character 8
Residual random jitter RJTX 0.09 2 ps-rms VID = 500 mVpp, UI = 167 ps, K28.7 control character 8

CAD (KiCad official)

  • Symbol: SN75LVCP601RTJR
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: sn75lvcp601rtjr-etched.step / sn75lvcp601rtjr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn75lvcp601rtjr.step / sn75lvcp601rtjr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 5a7c2e15ad114f17, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF