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SN75LBC184M
Public Made by Adomby adom
HGSEMI RS-485/RS-422 ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN75LBC184M
HGSEMI · RS-485/RS-422 ICs · SOIC-8
SN75LBC184M from HGSEMI, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | R | output | Receiver output, driven high when the inputs are open-circuit (fail-safe) and high-impedance when RE is high; rated VOH 2.8 V min at -8 mA and VOL 0.4 V max at 4 mA. |
| 2 | RE | input | Active-low receiver enable; low enables the receiver and high puts R in high impedance, with VIH 2 V min and VIL 0.8 V max. |
| 3 | DE | input | Driver enable; high enables the driver outputs A and B and low puts them in high impedance, with VIH 2 V min and VIL 0.8 V max. |
| 4 | D | input | Driver data input; high drives A high and B low, low drives A low and B high when DE is high, with VIH 2 V min and VIL 0.8 V max. |
| 5 | GND | power_in | Ground, the network ground reference for all voltages except differential bus voltage. |
| 6 | A | bidirectional | Non-inverting driver output and receiver input bus terminal, with transient voltage suppression and bus voltage range of -7 V to 12 V recommended. |
| 7 | B | bidirectional | Inverting driver output and receiver input bus terminal, with transient voltage suppression and bus voltage range of -7 V to 12 V recommended. |
| 8 | VCC | power_in | Supply voltage, recommended 4.75 V to 5.25 V (5 V typical), absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.75 | 5 | 5.25 | V | 5 | |
| Voltage at any bus terminal | VI or VIC | -7 | 12 | V | separately or common mode | 5 | |
| High-level input voltage | VIH | 2 | V | D, DE, and RE | 5 | ||
| Low-level input voltage | VIL | 0.8 | V | D, DE, and RE | 5 | ||
| Differential input voltage | /VID/ | 12 | V | 5 | |||
| High-level output current, driver | IOH | -60 | mA | Driver | 5 | ||
| High-level output current, receiver | IOH | -8 | mA | Receiver | 5 | ||
| Low-level output current, driver | IOL | 60 | mA | Driver | 5 | ||
| Low-level output current, receiver | IOL | 4 | mA | Receiver | 5 | ||
| Operating free-air temperature | TA | 0 | 70 | °C | SN75LBC184 | 5 | |
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Continuous voltage range at any bus terminal | -15 | 15 | V | 4 | |||
| Data input/output voltage | -0.3 | 7 | V | 4 | |||
| Receiver output current | IO | -20 | 20 | mA | 4 | ||
| ESD contact discharge IEC61000-4-2 | 30 | KV | A,B,ND | 4 | |||
| ESD air discharge IEC61000-4-2 | 15 | KV | A,B,ND | 4 | |||
| ESD human body model | 15 | KV | A,B,ND | 4 | |||
| Lead temperature | 260 | ℃ | Soldering, 10 seconds | 4 | |||
| Power rating M package | 1150 | mW | TA ≤ 25℃; derating 9.2 mW/℃ above 25℃ | 5 | |||
| Power rating M package | 736 | mW | TA = 70°C | 5 | |||
| Driver supply current, enabled | ICC | 12 | 25 | mA | DE = RE = 5 V, No Load | 6 | |
| Driver supply current, disabled | ICC | 175 | 300 | µA | DE = 0 V, RE = 5 V, No Load | 6 | |
| High-level input current | IIH | 50 | µA | VI = 2.4 V | 6 | ||
| Low-level input current | IIL | -50 | µA | VI = 0.4 V | 6 | ||
| Short-circuit output current | IOS | -250 | -120 | mA | VO = −7 V | 6 | |
| Short-circuit output current | IOS | 250 | mA | VO = VCC | 6 | ||
| Output voltage | VO | 0 | 5 | V | IO = 0 (max printed as VCC) | 6 | |
| Peak-to-peak change in common-mode output voltage | VOC(PP) | 0.8 | V | See Figures 5 and 6 | 6 | ||
| Common-mode output voltage | VOC | 1 | 3 | V | See Figure 4 | 6 | |
| Change in common-mode steady-state output voltage | ΔVOC(SS) | 0.1 | V | See Figure 5 | 6 | ||
| Differential output voltage magnitude | /VOD/ | 1.5 | 6 | V | IO = 0 | 6 | |
| Differential output voltage magnitude | /VOD/ | 1.5 | V | RL = 54Ω, See Figure 4 | 6 | ||
| Change in differential voltage magnitude between logic states | Δ/VOD/ | 0.1 | V | RL = 54Ω | 6 | ||
| Driver differential output delay time, low-to-high | td(DH) | 1.3 | µs | RL = 54Ω, CL = 50 pF, See Figure 5 | 6 | ||
| Driver differential output delay time, high-to-low | td(DL) | 1.3 | µs | RL = 54Ω, CL = 50 pF, See Figure 5 | 6 | ||
| Driver propagation delay, low-to-high | tPLH | 0.5 | 1.3 | µs | RL = 54Ω, CL = 50 pF, See Figure 5 | 6 | |
| Driver propagation delay, high-to-low | tPHL | 0.5 | 1.3 | µs | RL = 54Ω, CL = 50 pF, See Figure 5 | 6 | |
| Driver pulse skew | tsk(p) | 75 | 150 | ns | RL = 54Ω, CL = 50 pF, See Figure 5 | 6 | |
| Driver rise time, single ended | tr | 0.25 | 1.2 | µs | RL = 54Ω, CL = 50 pF, See Figure 5 | 6 | |
| Driver fall time, single ended | tf | 0.25 | 1.2 | µs | RL = 54Ω, CL = 50 pF, See Figure 5 | 6 | |
| Driver output enable time to high level | tPZH | 3.5 | µs | RL = 110Ω See Figure 2 | 6 | ||
| Driver output enable time to low level | tPZL | 3.5 | µs | RL = 110Ω See Figure 3 | 6 | ||
| Driver output disable time from high level | tPHZ | 2 | µs | RL = 110Ω See Figure 2 | 6 | ||
| Driver output disable time from low level | tPLZ | 2 | µs | RL = 110Ω See Figure 3 | 6 | ||
| Receiver supply current (total package) | ICC | 3.9 | mA | DE = RE = 0 V, No Load | 7 | ||
| Receiver supply current, disabled | ICC | 300 | µA | RE = 5 V, No Load, DE = 0 V, No Load | 7 | ||
| Input current | II | 250 | µA | Other input = 0 V, VI = 12 V | 7 | ||
| Input current | II | -200 | µA | Other input = 0 V, VI = −7V | 7 | ||
| High-impedance-state output current | IOZ | -100 | 100 | µA | VO = 0.4 V to 2.4 V | 7 | |
| Input hysteresis voltage | Vhys | 70 | mV | 7 | |||
| Positive-going input threshold voltage | VIT+ | 200 | mV | 7 | |||
| Negative-going input threshold voltage | VIT− | -200 | mV | 7 | |||
| High-level output voltage | VOH | 2.8 | V | IOH = − 8 mA Figure 7 | 7 | ||
| Low-level output voltage | VOL | 0.4 | V | IOL = 4 mA Figure 7 | 7 | ||
| Receiver propagation delay, low-to-high | tPLH | 150 | ns | CL = 50 pF, See Figure 7 | 7 | ||
| Receiver propagation delay, high-to-low | tPHL | 150 | ns | CL = 50 pF, See Figure 7 | 7 | ||
| Receiver pulse skew | tsk(p) | 50 | ns | CL = 50 pF, See Figure 7 | 7 | ||
| Receiver rise time, single ended | tr | 20 | ns | See Figure 7 | 7 | ||
| Receiver fall time, single ended | tf | 20 | ns | See Figure 7 | 7 | ||
| Receiver output enable time to high level | tPZH | 100 | ns | See Figure 8 | 7 | ||
| Receiver output enable time to low level | tPZL | 100 | ns | See Figure 8 | 7 |
CAD (KiCad official)
- Symbol:
SN75LBC184M - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
sn75lbc184m-etched.step/sn75lbc184m-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn75lbc184m.step/sn75lbc184m.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (18 pp, sha256
9096a171de5a8521, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).