component
SN75LBC184DR-HXY
Public Made by Adomby adom
HXY MOSFET RS-485/RS-422 ICs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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SN75LBC184DR-HXY
HXY MOSFET · RS-485/RS-422 ICs · SOP-8
SN75LBC184DR-HXY from HXY MOSFET, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | R | output | Receiver data output (digital output); high-impedance when RE is high, and high when the bus inputs are open (fail-safe). |
| 2 | RE | input | Active-LOW receiver enable digital input; VIH min 2 V, VIL max 0.8 V. |
| 3 | DE | input | Active-HIGH driver enable digital input; VIH min 2 V, VIL max 0.8 V. |
| 4 | D | input | Driver data input (digital input); VIH min 2 V, VIL max 0.8 V. |
| 5 | GND | power_in | Local device ground reference potential. |
| 6 | A | bidirectional | Bus input/output, driver output or receiver input (complementary to B); bus voltage range -7 V to 12 V. |
| 7 | B | bidirectional | Bus input/output, driver output or receiver input (complementary to A); bus voltage range -7 V to 12 V. |
| 8 | VCC | power_in | Supply pin, 4.75 V to 5.25 V supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HXY MOSFET |
| Package | SOP-8 |
| Category | Communication Interface Chip |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| Continuous voltage range at any bus terminal | -15 | 15 | V | 3 | |||
| Data input/output voltage | -0.3 | 7 | V | 3 | |||
| Receiver output current | IO | -20 | 20 | mA | 3 | ||
| Storage temperature | Tstg | 160 | °C | 3 | |||
| Supply voltage | VCC | 4.75 | 5 | 5.25 | V | 4 | |
| Voltage at any bus terminal (separately or common mode) | VI or VIC | -7 | 12 | V | 4 | ||
| High-level input voltage D, DE, RE | VIH | 2 | V | 4 | |||
| Low-level input voltage D, DE, RE | VIL | 0.8 | V | 4 | |||
| Differential input voltage | /VID/ | 12 | V | 4 | |||
| High-level output current, driver | IOH | -60 | mA | Driver | 4 | ||
| High-level output current, receiver | IOH | -8 | mA | Receiver | 4 | ||
| Low-level output current, driver | IOL | 60 | mA | Driver | 4 | ||
| Low-level output current, receiver | IOL | 4 | mA | Receiver | 4 | ||
| Operating free-air temperature SN75LBC184 | TA | 0 | 70 | °C | SN75LBC184 | 4 | |
| Junction-to-ambient thermal resistance | RθJA | 172.4 | °C/W | D [SOP-8] | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 42.5 | °C/W | D [SOP-8] | 4 | ||
| Junction-to-board thermal resistance | RθJB | 41.4 | °C/W | D [SOP-8] | 4 | ||
| Driver supply current, enabled | ICC | 12 | 25 | mA | DE = RE = 5 V No Load | 5 | |
| Driver supply current, disabled | ICC | 175 | 300 | μA | DE = 0 V, RE = 5 V, No Load | 5 | |
| High-level input current (D, DE, RE) | IIH | 50 | μA | VI = 2.4 V | 5 | ||
| Low-level input current (D, DE, RE) | IIL | -50 | μA | VI = 0.4 V | 5 | ||
| Short-circuit output current | IOS | -250 | -120 | 250 | mA | VO = -7 V; VO = VCC; VO = 12 V | 5 |
| Output voltage | VO | 0 | V | IO = 0 | 5 | ||
| Peak-to-peak change in common-mode output voltage | VOC(PP) | 0.8 | V | See Figure 9 and Figure 10 | 5 | ||
| Common-mode output voltage | VOC | 1 | 3 | V | See Figure 8 | 5 | |
| Change in common-mode steady-state output voltage | /ΔVOC(SS)/ | 0.1 | V | See Figure 10 | 5 | ||
| Differential output voltage magnitude | /VOD/ | 1.5 | 6 | V | IO = 0 | 5 | |
| Differential output voltage magnitude | /VOD/ | 1.5 | V | RL = 54 Ω, See Figure 8 | 5 | ||
| Change in differential voltage magnitude between logic states | Δ/VOD/ | 0.1 | V | RL = 54 Ω | 5 | ||
| Receiver supply current | ICC | 3.9 | mA | DE = RE = 0 V, No Load | 5 | ||
| Receiver supply current, disabled | ICC | 300 | μA | RE = 5 V, DE = 0 V, No Load | 5 | ||
| Input current | II | -200 | 250 | μA | VI = 12 V; VI = 12 V, VCC = 0; VI = -7 V; VI = -7 V, VCC = 0; other input = 0 V | 5 | |
| High-impedance-state output current | IOZ | -100 | 100 | μA | VO = 0.4 V to 2.4 V | 5 | |
| Input hysteresis voltage | Vhys | 70 | mV | 5 | |||
| Positive-going input threshold voltage | VIT+ | 200 | V | 5 | |||
| Negative-going input threshold voltage | VIT- | -200 | mV | 5 | |||
| High-level output voltage | VOH | 2.8 | V | IOH = -8 mA, See Figure 11 | 5 | ||
| Low-level output voltage | VOL | 0.4 | V | IOL = 4 mA, See Figure 11 | 5 | ||
| Driver differential output delay time, low-to-high | td(DH) | 1.3 | μs | RL = 54 Ω, CL = 50 pF, See Figure 9 | 4 | ||
| Driver differential output delay time, high-to-low | td(DL) | 1.3 | μs | RL = 54 Ω, CL = 50 pF, See Figure 9 | 4 | ||
| Driver propagation delay time, low-to-high | tPLH | 0.5 | 1.3 | μs | RL = 54 Ω, CL = 50 pF, See Figure 9 | 4 | |
| Driver propagation delay time, high-to-low | tPHL | 0.5 | 1.3 | μs | RL = 54 Ω, CL = 50 pF, See Figure 9 | 4 | |
| Driver pulse skew | tsk(p) | 75 | 150 | ns | RL = 54 Ω, CL = 50 pF, See Figure 9 | 4 | |
| Driver rise time, single-ended | tr | 0.25 | 1.2 | μs | RL = 54 Ω, CL = 50 pF, See Figure 9 | 4 | |
| Driver fall time, single-ended | tf | 0.25 | 1.2 | μs | RL = 54 Ω, CL = 50 pF, See Figure 9 | 4 | |
| Driver output enable time to high level | tPZH | 3.5 | μs | RL = 110 Ω See Figure 6 | 4 | ||
| Driver output enable time to low level | tPZL | 3.5 | μs | RL = 110 Ω See Figure 7 | 4 | ||
| Driver output disable time from high level | tPHZ | 2 | μs | RL = 110 Ω See Figure 6 | 4 | ||
| Driver output disable time from low level | tPLZ | 2 | μs | RL = 110 Ω See Figure 7 | 4 | ||
| Receiver propagation delay time, low-to-high | tPLH | 150 | ns | CL = 50 pF, See Figure 11 | 6 | ||
| Receiver propagation delay time, high-to-low | tPHL | 150 | ns | CL = 50 pF, See Figure 11 | 6 | ||
| Receiver pulse skew | tsk(p) | 50 | ns | CL = 50 pF, See Figure 11 | 6 | ||
| Receiver rise time, single-ended | tr | 20 | ns | See Figure 11 | 6 | ||
| Receiver fall time, single-ended | tf | 20 | ns | See Figure 11 | 6 | ||
| Receiver output enable time to high level | tPZH | 100 | ns | See Figure 12 | 6 | ||
| Receiver output enable time to low level | tPZL | 100 | ns | See Figure 12 | 6 | ||
| Receiver output disable time from high level | tPHZ | 100 | ns | See Figure 12 | 6 | ||
| Receiver output disable time from low level | tPLZ | 100 | ns | See Figure 12 | 6 |
CAD (KiCad official)
- Symbol:
SN75LBC184DR-HXY - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
sn75lbc184dr-hxy-etched.step/sn75lbc184dr-hxy-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn75lbc184dr-hxy.step/sn75lbc184dr-hxy.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HXY MOSFET datasheet (14 pp, sha256
47b14d9bbbd36ccc, retrieved 2026-10-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).