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SN75DP159RSBR

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Texas Instruments Video Interface ICs, WQFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232sn75dp159rsbrfactory-2.0.0extractor-text

Verified SN75DP159RSBR

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN75DP159RSBR · WQFN-40-EP(5x5) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 66-page datasheet
  • ✓distributor: lcsc C1849438, digikey 296-SN75DP159RSBRTR-ND, mouser 595-SN75DP159RSBR
  • ✓family: QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-c49492td/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.63)
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn75dp159rsbr.kicad_sym✓ sn75dp159rsbr.kicad_mod✓ sn75dp159rsbr.step
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SN75DP159RSBR

Texas Instruments · Video Interface ICs · WQFN-40-EP(5x5)

SN75DP159RSBR from Texas Instruments, in a WQFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN_D2p input Channel 2 differential input, positive (fail safe).
2 IN_D2n input Channel 2 differential input, negative (fail safe).
3 HPD_SRC output Hot plug detect output to the source.
4 IN_D1p input Channel 1 differential input, positive (fail safe).
5 IN_D1n input Channel 1 differential input, negative (fail safe).
6 IN_D0p input Channel 0 differential input, positive (fail safe).
7 IN_D0n input Channel 0 differential input, negative (fail safe).
8 I2C_EN/PIN input High puts the device into I2C control mode; low puts it into pin strap mode.
9 IN_CLKp input Clock differential input, positive (fail safe).
10 IN_CLKn input Clock differential input, negative (fail safe).
11 VCC power_in 3.3-V power supply (3 V min, 3.3 V nom, 3.6 V max).
12 VDD power_in 1.1-V power supply (1.00 V min, 1.1 V nom, 1.27 V max).
13 SCL_CTL input I2C clock signal; when I2C_EN/PIN = Low, pin strapping takes priority and those functions cannot be changed by I2C.
14 SDA_CTL bidirectional I2C data signal; when I2C_EN/PIN = Low, pin strapping takes priority and those functions cannot be changed by I2C.
15 GND power_in Ground.
16 PRE_SEL input 3-level de-emphasis strap when I2C_EN/PIN = Low: L = -2 dB, no connect = 0 dB, H = reserved.
17 EQ_SEL/A0 input 3-level receive equalization strap when I2C_EN/PIN = Low (L = fixed 7.5 dB, no connect = adaptive, H = fixed 14 dB); I2C address bit 1 when I2C_EN/PIN = High.
18 Vsadj input TMDS-compliant voltage swing control; connect a nominal resistor to GND (7.06 kΩ nominal, 4.5 to 7.5 kΩ).
19 VDD power_in 1.1-V power supply (1.00 V min, 1.1 V nom, 1.27 V max).
20 VDD power_in 1.1-V power supply (1.00 V min, 1.1 V nom, 1.27 V max).
21 OUT_CLKn output TMDS data clock differential output, negative (fail safe).
22 OUT_CLKp output TMDS data clock differential output, positive (fail safe).
23 HDMI_SEL/A1 input When I2C_EN/PIN = Low, High configures the device for DVI and Low for HDMI; when I2C_EN/PIN = High, I2C address bit 2; weak internal pull down.
24 OUT_D0n output TMDS data 0 differential output, negative (fail safe).
25 OUT_D0p output TMDS data 0 differential output, positive (fail safe).
26 OUT_D1n output TMDS data 1 differential output, negative (fail safe).
27 OUT_D1p output TMDS data 1 differential output, positive (fail safe).
28 HPD_SNK input Hot plug detect input from the sink (fail safe); absolute maximum voltage 6 V.
29 OUT_D2n output TMDS data 2 differential output, negative (fail safe).
30 OUT_D2p output TMDS data 2 differential output, positive (fail safe).
31 VDD power_in 1.1-V power supply (1.00 V min, 1.1 V nom, 1.27 V max).
32 SCL_SNK bidirectional Sink side TMDS port bidirectional DDC clock line (fail safe).
33 SDA_SNK bidirectional Sink side TMDS port bidirectional DDC data line (fail safe).
34 SLEW_CTL input 3-level slew rate strap when I2C_EN/PIN = Low (H = fastest data rate, L = 5 ps slow, no connect = 10 ps slow); slew rate is controlled through I2C when I2C_EN/PIN = High.
35 GND power_in Ground.
36 OE input Operation enable/reset: L = power-down mode, H = normal operation; internal weak pullup (150 to 250 kΩ) and device resets on an H to L transition.
37 VCC power_in 3.3-V power supply (3 V min, 3.3 V nom, 3.6 V max).
38 SCL_SRC bidirectional Source side TMDS port bidirectional DDC clock line (fail safe).
39 SDA_SRC bidirectional Source side TMDS port bidirectional DDC data line (fail safe).
40 VDD power_in 1.1-V power supply (1.00 V min, 1.1 V nom, 1.27 V max).
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40-EP(5x5)
Category Communication Interface Chip/UART/485/232
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC VCC 3 3.3 3.6 V 8
Supply voltage VDD VDD 1 1.1 1.27 V 8
Operating free-air temperature SN75DP159 TA 0 85 °C SN75DP159 8
Case temperature RSB package TCASE 93.5 °C RSB package 8
Peak-to-peak input differential voltage VID_PP 75 1200 mV 8
Input common mode voltage VIC 0 2 V 8
AC coupling capacitance CAC 75 100 200 nF 8
VSADJ bias resistor VSADJ 4.5 7.06 7.5 kΩ TMDS-compliant swing voltage bias resistor 8
Control pin DC input voltage VI-DC -0.3 3.6 V Control pins 8
Pullup resistance on OE pin ROEPU 150 250 kΩ 8
Supply voltage VCC VCC -0.3 4 V 7
Supply voltage VDD VDD -0.3 1.4 V 7
TMDS outputs voltage OUT_Dx -0.3 4 V 7
HPD_SNK, SDA_SNK, SCL_SNK voltage -0.3 6 V 7
Storage temperature Tstg -65 150 °C 7
ESD HBM V(ESD) -2000 2000 V HBM, all pins 7
ESD CDM V(ESD) -500 500 V CDM, all pins 7
Junction-to-ambient thermal resistance RθJA 37.3 °C/W RSB (WQFN) 40 pins 8
Junction-to-case (top) thermal resistance RθJC(top) 23.1 °C/W RSB, High-K board 8
Junction-to-board thermal resistance RθJB 9.9 °C/W RSB, High-K board 8
Junction-to-case (bottom) thermal resistance RθJC(bot) 3.2 °C/W RSB 8
Device power dissipation (retimer) PD1 435 600 mW OE = H, 6Gbps TMDS pattern, VSadj = 7.06 kΩ 9
Device power dissipation (redriver) PD2 215 400 mW OE = H, 6Gbps TMDS pattern, VSadj = 7.06 kΩ 9
Device power in power down PSD1 10 30 mW OE = L, VSadj = 7.06 kΩ 9
VCC supply current retimer mode ICC1 35 50 mA OE = H, 6Gbps TMDS pattern, SLEW_CTL = H 9
VDD supply current retimer mode IDD1 295 325 mA OE = H, 6Gbps TMDS pattern, SLEW_CTL = H 9
VCC supply current redriver mode ICC2 8 20 mA OE = H, 6Gbps TMDS pattern, SLEW_CTL = H 9
VDD supply current redriver mode IDD2 170 250 mA OE = H, 6Gbps TMDS pattern, SLEW_CTL = H 9
Power-down current 3.3-V rail ISD1 2 5 mA OE = L, 3.3-V rail 9
Power-down current 1.1-V rail ISD1 3.5 10 mA OE = L, 1.1-V rail 9
Input differential termination impedance RINT 80 100 120 Ω 10
Data lane data rate DR_RX_DATA 0.25 6 Gbps 10
Single-ended output voltage swing on data lane VSWING_DA 400 500 600 mV PRE_SEL = NC; TX_TERM_CTL = H/NC/L; SLEW_CTL = H; OE = H; VSadj = 7.06-kΩ 11
Output differential voltage before pre-emphasis VOD(PP) 800 1200 mV Vsadj = 7.06-kΩ; PRE_SEL = Z 11
Steady-state output differential voltage VOD(SS) 600 1050 mV Vsadj = 7.06-kΩ; PRE_SEL = L 11
Failsafe condition leakage current ILEAK 45 µA VCC = 0-V; VDD = 0-V; output pulled to 3.3 V through 50-Ω resistors 11
Source termination resistance for HDMI 2.0 RTERM 75 150 Ω 11
HPD_SNK high-level input voltage VIH 2.1 V HPD_SNK 12
HPD_SNK low-level input voltage VIL 0.8 V HPD_SNK 12
HPD_SRC high-level output voltage VOH 2.4 3.6 V IOH = -500-µA; HPD_SRC 12
HPD_SRC low-level output voltage VOL 0 0.1 V IOL = 500-µA; HPD_SRC 12
HPD input termination to GND RpdHPD 150 190 220 kΩ VCC = 0-V 12
Propagation delay HPD_SNK to HPD_SRC tPD(HPD) 40 120 ns See 图 14; not valid during switching time 15
Data retimer PLL bandwidth PLLBW 0.4 1 MHz Default loop bandwidth setting 13
Retimer acquisition time tACQ 180 µs Input clock frequency detection and retimer acquisition time 13

CAD (KiCad official)

  • Symbol: SN75DP159RSBR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: WQFN-40-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: sn75dp159rsbr-etched.step / sn75dp159rsbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn75dp159rsbr.step / sn75dp159rsbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (66 pp, sha256 372df67cd947c9c6, retrieved 2026-10-31, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF