component

SN75DP159RGZT

Public Made by Adom

by adom

Texas Instruments Clock And Data Recovery / Retiming, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock-timingsn75dp159rgztfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3d ago
viewers sn75dp159rgzt: viewers · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Initial commit: component/sn75dp159rgzt · Ray 3d ago
sn75dp159rgzt-etched.glb sn75dp159rgzt: factory component page (tier=lcsc) · Ray 3d ago
sn75dp159rgzt-etched.step sn75dp159rgzt: factory component page (tier=lcsc) · Ray 3d ago
sn75dp159rgzt-hero.glb Publish 0.1.0 · Ray 3d ago
sn75dp159rgzt-hero.overlay.json Publish 0.1.0 · Ray 3d ago
sn75dp159rgzt.glb Publish 0.1.0 · Ray 3d ago
sn75dp159rgzt.kicad_mod Publish 0.1.0 · Ray 3d ago
sn75dp159rgzt.kicad_sym Publish 0.1.0 · Ray 3d ago
sn75dp159rgzt.lbr Publish 0.1.0 · Ray 3d ago
sn75dp159rgzt.step Publish 0.1.0 · Ray 3d ago

SN75DP159RGZT

Texas Instruments · Clock And Data Recovery / Retiming · VQFN-48-EP(7x7)

SN75DP159RGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SWAP/POL input 3-level input lane SWAP and polarity control pin; when I2C_EN/PIN = Low: H selects polarity swap (retimer only), L selects lane swap, No Connect is normal operation.
2 IN_D2p input Channel 2 differential input, AC-coupled TMDS or DisplayPort dual-mode physical level signal.
3 IN_D2n input Channel 2 differential input, AC-coupled TMDS or DisplayPort dual-mode physical level signal.
4 HPD_SRC output Hot plug detect output for source-side signaling.
5 IN_D1p input Channel 1 differential input, AC-coupled TMDS or DisplayPort dual-mode physical level signal.
6 IN_D1n input Channel 1 differential input, AC-coupled TMDS or DisplayPort dual-mode physical level signal.
7 GND power_in Ground connection.
8 IN_D0p input Channel 0 differential input, AC-coupled TMDS or DisplayPort dual-mode physical level signal.
9 IN_D0n input Channel 0 differential input, AC-coupled TMDS or DisplayPort dual-mode physical level signal.
10 I2C_EN/PIN input I2C enable/pin strap mode selection; H puts device into I2C control mode, L puts device into pin strap mode.
11 IN_CLKp input Clock differential input, AC-coupled TMDS or DisplayPort dual-mode physical level signal.
12 IN_CLKn input Clock differential input, AC-coupled TMDS or DisplayPort dual-mode physical level signal.
13 VCC power_in 3.3-V power supply.
14 VDD power_in 1.1-V power supply.
15 SCL_CTL input I2C clock signal; note that pin strapping takes priority when I2C_EN/PIN = Low.
16 SDA_CTL bidirectional I2C data signal; note that pin strapping takes priority when I2C_EN/PIN = Low.
17 NC unconnected No connect pin; blue pin names only in SNx5DP159 RGZ package.
18 CEC_EN output CEC control pin for dongle applications; blue pin names only in SNx5DP159 RGZ package.
19 GND power_in Ground connection.
20 PRE_SEL input 3-level de-emphasis pin strap when I2C_EN/PIN = Low; L = -2 dB, No Connect = 0 dB, H = reserved.
21 EQ_SEL/A0 input 3-level input receive equalization pin strap when I2C_EN/PIN = Low (L: 7.5 dB fixed; No Connect: adaptive; H: 14 dB fixed); address bit 0 when I2C_EN/PIN = High.
22 Vsadj input TMDS-compliant voltage swing control via nominal resistor to GND; recommend 6.4 kΩ for best transmit eye with minimum intra-pair skew.
23 VDD power_in 1.1-V power supply.
24 VDD power_in 1.1-V power supply.
25 OUT_CLKn output TMDS data clock differential output.
26 OUT_CLKp output TMDS data clock differential output.
27 HDMI_SEL/A1 input HDMI_SEL when I2C_EN/PIN = Low (H: DVI configured; L: HDMI configured with adaptor ID block readable); address bit 1 when I2C_EN/PIN = High; weak internal pull down.
28 OUT_D0n output TMDS data 0 differential output.
29 OUT_D0p output TMDS data 0 differential output.
30 GND power_in Ground connection.
31 OUT_D1n output TMDS data 1 differential output.
32 OUT_D1p output TMDS data 1 differential output.
33 HPD_SNK input Failsafe hot plug detect input from sink.
34 OUT_D2n output TMDS data 2 differential output.
35 OUT_D2p output TMDS data 2 differential output.
36 TX_TERM_CTL input 3-level transmit termination control when I2C_EN/PIN = Low; H: no termination, L: 75-150Ω, No Connect: auto-select based on data rate; blue pin names only in RGZ package.
37 VDD power_in 1.1-V power supply.
38 SCL_SNK bidirectional Failsafe sink side TMDS port bidirectional DDC data line.
39 SDA_SNK bidirectional Failsafe sink side TMDS port bidirectional DDC data line.
40 SLEW_CTL input 3-level slew rate control when I2C_EN/PIN = Low; H: fastest, L: 5 ps slow, No Connect: 10 ps slow; slew rate controlled via I2C when I2C_EN/PIN = High.
41 GND power_in Ground connection.
42 OE input Operation enable/reset pin; L: power-down mode with outputs high impedance, H: normal operation; internal weak pullup (150-250 kΩ); must be low for minimum 100 µs before assertion.
43 VCC power_in 3.3-V power supply.
44 AUX_SRCn bidirectional Source side bidirectional DisplayPort auxiliary for I2C-over-AUX; blue pin names only in SNx5DP159 RGZ package.
45 AUX_SRCp bidirectional Source side bidirectional DisplayPort auxiliary for I2C-over-AUX with 1.56V max differential voltage; blue pin names only in SNx5DP159 RGZ package.
46 SCL_SRC bidirectional Failsafe source side TMDS port bidirectional DDC data line.
47 SDA_SRC bidirectional Failsafe source side TMDS port bidirectional DDC data line.
48 VDD power_in 1.1-V power supply.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Clock/Timing
Pins 49

CAD (KiCad official)

  • Symbol: SN75DP159RGZT
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: sn75dp159rgzt-etched.step / sn75dp159rgzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn75dp159rgzt.step / sn75dp159rgzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (62 pp, sha256 2c62dedfbca0b0cc, retrieved 2026-10-03, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF