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SN75DP159RGZR

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Texas Instruments Clock And Data Recovery / Retiming, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN75DP159RGZR

Texas Instruments · Clock And Data Recovery / Retiming · VQFN-48-EP(7x7)

SN75DP159RGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SWAP/POL input Tri-level input lane swap and polarity control used when I2C_EN/PIN is Low: H = receive lane polarity swap (retimer mode only), L = receive lanes swap (retimer and redriver modes), NC = normal operation.
2 IN_D2p input Channel 2 positive leg of the fail-safe AC-coupled main-link differential input, with a peak-to-peak differential input voltage of 75 to 1200 mV.
3 IN_D2n input Channel 2 negative leg of the fail-safe AC-coupled main-link differential input, with a peak-to-peak differential input voltage of 75 to 1200 mV.
4 HPD_SRC output Hot plug detect output toward the source.
5 IN_D1p input Channel 1 positive leg of the fail-safe AC-coupled main-link differential input, with a peak-to-peak differential input voltage of 75 to 1200 mV.
6 IN_D1n input Channel 1 negative leg of the fail-safe AC-coupled main-link differential input, with a peak-to-peak differential input voltage of 75 to 1200 mV.
7 GND power_in Ground.
8 IN_D0p input Channel 0 positive leg of the fail-safe AC-coupled main-link differential input, with a peak-to-peak differential input voltage of 75 to 1200 mV.
9 IN_D0n input Channel 0 negative leg of the fail-safe AC-coupled main-link differential input, with a peak-to-peak differential input voltage of 75 to 1200 mV.
10 I2C_EN/PIN input Selects the control mode: H = I2C control mode, L = pin-strap mode, in which pin strapping takes priority and cannot be changed over I2C.
11 IN_CLKp input Positive leg of the fail-safe clock differential input.
12 IN_CLKn input Negative leg of the fail-safe clock differential input.
13 VCC power_in 3.3 V power supply; recommended 3.0 to 3.6 V, absolute maximum 4 V.
14 VDD power_in 1.1 V power supply; recommended 1.00 to 1.27 V, absolute maximum 1.4 V.
15 SCL_CTL input I2C clock signal for I2C control mode; when I2C_EN/PIN is Low, pin straps take priority over I2C.
16 SDA_CTL bidirectional I2C data signal for I2C control mode; when I2C_EN/PIN is Low, pin straps take priority over I2C.
17 NC unconnected No connect.
18 CEC_EN output CEC control pin for dongle applications; it may be left unconnected or routed to control a CEC enable FET.
19 GND power_in Ground.
20 PRE_SEL input Tri-level de-emphasis strap when I2C_EN/PIN is Low: L = -2 dB, NC = 0 dB, H = reserved.
21 EQ_SEL/A0 input Tri-level input receive equalization strap when I2C_EN/PIN is Low (L = fixed 7.5 dB, NC = adaptive, H = fixed 14 dB); when I2C_EN/PIN is High it is I2C address bit A0.
22 Vsadj input TMDS-compliant voltage swing control resistor to GND; recommended 4.5 to 7.5 kΩ with 7.06 kΩ nominal.
23 VDD power_in 1.1 V power supply; recommended 1.00 to 1.27 V, absolute maximum 1.4 V.
24 VDD power_in 1.1 V power supply; recommended 1.00 to 1.27 V, absolute maximum 1.4 V.
25 OUT_CLKn output Negative leg of the TMDS clock differential output (fail-safe).
26 OUT_CLKp output Positive leg of the TMDS clock differential output (fail-safe).
27 HDMI_SEL/A1 input When I2C_EN/PIN is Low: H = device configured for DVI, L = device configured for HDMI, with a weak internal pull-down; when I2C_EN/PIN is High it is I2C address bit A1.
28 OUT_D0n output Negative leg of TMDS data channel 0 differential output (fail-safe).
29 OUT_D0p output Positive leg of TMDS data channel 0 differential output (fail-safe).
30 GND power_in Ground.
31 OUT_D1n output Negative leg of TMDS data channel 1 differential output (fail-safe).
32 OUT_D1p output Positive leg of TMDS data channel 1 differential output (fail-safe).
33 HPD_SNK input Fail-safe hot plug detect input from the sink.
34 OUT_D2n output Negative leg of TMDS data channel 2 differential output (fail-safe).
35 OUT_D2p output Positive leg of TMDS data channel 2 differential output (fail-safe).
36 TX_TERM_CTL input Tri-level transmit termination control when I2C_EN/PIN is Low: H = no transmit termination, L = 75 to about 150 Ω, NC = automatic selection.
37 VDD power_in 1.1 V power supply; recommended 1.00 to 1.27 V, absolute maximum 1.4 V.
38 SCL_SNK bidirectional Fail-safe sink-side TMDS port bidirectional DDC line, with absolute maximum rating of -0.3 to 6 V.
39 SDA_SNK bidirectional Fail-safe sink-side TMDS port bidirectional DDC data line, with absolute maximum rating of -0.3 to 6 V.
40 SLEW_CTL input Tri-level output slew-rate control when I2C_EN/PIN is Low: H = fastest data rate, L = 5 ps slow, NC = 10 ps slow.
41 GND power_in Ground.
42 OE input Operation enable/reset: L = power-down mode, H = normal operation; the internal 150 to 250 kΩ pull-up resets the device when OE transitions from H to L.
43 VCC power_in 3.3 V power supply; recommended 3.0 to 3.6 V, absolute maximum 4 V.
44 AUX_SRCn bidirectional Negative leg of the source-side DisplayPort auxiliary channel used for I2C-over-AUX (RGZ package only).
45 AUX_SRCp bidirectional Positive leg of the source-side DisplayPort auxiliary channel used for I2C-over-AUX (RGZ package only).
46 SCL_SRC bidirectional Fail-safe source-side TMDS port bidirectional DDC line, with absolute maximum rating of -0.3 to 4 V.
47 SDA_SRC bidirectional Fail-safe source-side TMDS port bidirectional DDC data line, with absolute maximum rating of -0.3 to 4 V.
48 VDD power_in 1.1 V power supply; recommended 1.00 to 1.27 V, absolute maximum 1.4 V.
49 Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Clock/Timing
Pins 49

CAD (KiCad official)

  • Symbol: SN75DP159RGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: sn75dp159rgzr-etched.step / sn75dp159rgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn75dp159rgzr.step / sn75dp159rgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (62 pp, sha256 2c62dedfbca0b0cc, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF