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SN75DP149RSBT

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Texas Instruments Video Interface ICs, WQFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232sn75dp149rsbtfactory-2.0.0extractor-text
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Contents

README

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SN75DP149RSBT

Texas Instruments · Video Interface ICs · WQFN-40-EP(5x5)

SN75DP149RSBT from Texas Instruments, in a WQFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN_D2p input Channel 2 positive differential main link input (fail-safe); the recommended peak-to-peak differential input voltage is 75 to 1200 mV.
2 IN_D2n input Channel 2 negative differential main link input (fail-safe); the recommended peak-to-peak differential input voltage is 75 to 1200 mV.
3 HPD_SRC output Hot plug detect output on the source side.
4 IN_D1p input Channel 1 positive differential main link input (fail-safe); the recommended peak-to-peak differential input voltage is 75 to 1200 mV.
5 IN_D1n input Channel 1 negative differential main link input (fail-safe); the recommended peak-to-peak differential input voltage is 75 to 1200 mV.
6 IN_D0p input Channel 0 positive differential main link input (fail-safe); the recommended peak-to-peak differential input voltage is 75 to 1200 mV.
7 IN_D0n input Channel 0 negative differential main link input (fail-safe); the recommended peak-to-peak differential input voltage is 75 to 1200 mV.
8 I2C_EN/PIN input Selects I2C control mode when High and pin-strap mode when Low.
9 IN_CLKp input Positive clock differential input (fail-safe); the recommended peak-to-peak differential input voltage is 75 to 1200 mV.
10 IN_CLKn input Negative clock differential input (fail-safe); the recommended peak-to-peak differential input voltage is 75 to 1200 mV.
11 VCC power_in 3.3-V power supply; recommended range is 3.0 V to 3.6 V.
12 VDD power_in 1.1-V power supply; recommended range is 1.00 V to 1.27 V.
13 SCL_CTL input I2C clock signal for control; when I2C_EN/PIN is Low, pin strapping takes priority and these functions cannot be changed by I2C.
14 SDA_CTL bidirectional I2C data signal for control; when I2C_EN/PIN is Low, pin strapping takes priority and these functions cannot be changed by I2C.
15 GND power_in Ground.
16 PRE_SEL input Three-level de-emphasis select: Low gives -2 dB de-emphasis, no connect gives 0 dB, and High is reserved.
17 EQ_SEL/A0 input Three-level input receive equalization strap when I2C_EN/PIN is Low (Low = fixed 7.5 dB, no connect = adaptive EQ, High = fixed 14 dB); address bit 1 when I2C_EN/PIN is High.
18 Vsadj input TMDS-compliant voltage swing control; nominal resistor to GND of 6.5 kΩ per the recommended operating conditions.
19 VDD power_in 1.1-V power supply; recommended range is 1.00 V to 1.27 V.
20 VDD power_in 1.1-V power supply; recommended range is 1.00 V to 1.27 V.
21 OUT_CLKn output Negative TMDS data clock differential output (fail-safe).
22 OUT_CLKp output Positive TMDS data clock differential output (fail-safe).
23 HDMI_SEL/A1 input When I2C_EN/PIN is Low, High configures the device for DVI and Low configures it for HDMI; when High, it is address bit 2. Has a weak internal pull-down.
24 OUT_D0n output Negative TMDS data 0 differential output (fail-safe).
25 OUT_D0p output Positive TMDS data 0 differential output (fail-safe).
26 OUT_D1n output Negative TMDS data 1 differential output (fail-safe).
27 OUT_D1p output Positive TMDS data 1 differential output (fail-safe).
28 HPD_SNK input Fail-safe hot plug detect input on the sink side.
29 OUT_D2n output Negative TMDS data 2 differential output (fail-safe).
30 OUT_D2p output Positive TMDS data 2 differential output (fail-safe).
31 VDD power_in 1.1-V power supply; recommended range is 1.00 V to 1.27 V.
32 SCL_SNK bidirectional Fail-safe sink-side TMDS port bidirectional DDC clock line.
33 SDA_SNK bidirectional Fail-safe sink-side TMDS port bidirectional DDC data line.
34 SLEW_CTL input Three-level slew rate control when I2C_EN/PIN is Low: High = fastest data rate (default), Low = 5-ps slow, no connect = 10-ps slow; controlled through I2C when I2C_EN/PIN is High.
35 GND power_in Ground.
36 OE input Operation enable/reset: Low = power-down mode, High = normal operation; internal weak pullup resets the device on a High-to-Low transition.
37 VCC power_in 3.3-V power supply; recommended range is 3.0 V to 3.6 V.
38 SCL_SRC bidirectional Fail-safe source-side TMDS port bidirectional DDC clock line.
39 SDA_SRC bidirectional Fail-safe source-side TMDS port bidirectional DDC data line.
40 VDD power_in 1.1-V power supply; recommended range is 1.00 V to 1.27 V.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40-EP(5x5)
Category Communication Interface Chip/UART/485/232
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Vsadj resistor tolerance (1% precision recommended) -1 1 % 1% precision resistor recommended for Vsadj 26
AC coupling capacitance (main link inputs) CAC 75 100 200 nF 8
Supply voltage (absolute maximum) VCC -0.3 4 V 7
Supply voltage (absolute maximum) VDD -0.3 1.4 V 7
Main link input (IN_Dx AC-coupled mode) 1.56 V 7
TMDS outputs (OUT_Dx) -0.3 4 V 7
HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, HDMI_SEL/A1, EQ_SEL/A0, I2C_EN/PIN, SLEW_CTL, SDA_SRC, SCL_SRC voltage -0.3 4 V 7
HPD_SNK, SDA_SNK, SCL_SNK voltage -0.3 6 V 7
Storage temperature Tstg -65 150 °C 7
VCC supply voltage VCC 3 3.3 3.6 V 8
VDD supply voltage VDD 1 1.1 1.27 V 8
Case temperature for RSB package TCASE 93.5 °C RSB (WQFN) package 8
Operating free-air temperature (SN75DP149) TA 0 85 °C SN75DP149 8
Peak-to-peak input differential voltage VID_PP 75 1200 mV 8
Input common mode voltage VIC 0 2 V 8
Data rate dR 0.25 5 Gbps 8
DC input voltage (control pins) VI-DC -0.3 3.6 V 8
Low-level input voltage at OE VIL 0.8 V OE 8
Low-level input voltage at SLEW_CTL, PRE_SEL, EQ_SEL/A0, SWAP/POL VIL 0.3 V SLEW_CTL, PRE_SEL, EQ_SEL/A0, SWAP/POL 8
No connect input voltage at SLEW_CTL, PRE_SEL, EQ_SEL/A0, SWAP/POL VIM 1 1.2 1.4 V SLEW_CTL, PRE_SEL, EQ_SEL/A0, SWAP/POL no connect 8
High-level input voltage at SLEW_CTL, OE, PRE_SEL, EQ_SEL/A0, SWAP/POL VIH 2.6 V SLEW_CTL, OE, PRE_SEL, EQ_SEL/A0, SWAP/POL 8
Low-level output voltage VOL 0.4 V 8
High-level output voltage VOH 2.4 V 8
High-level input current IIH -30 30 µA 8
Low-level input current IIL -10 10 µA 8
Short circuit output current IOS -50 50 mA 8
High impedance output current IOZ 10 µA 8
Pullup resistance on OE pin ROEPU 150 250 kΩ 8
Device power dissipation (retimer mode) PD1 390 510 mW OE = H, HDMI_SEL = L, VCC = 3.3/3.6 V, VDD = 1.1/1.27 V, 3.4-Gbps TMDS pattern, VSadj = 6.5 kΩ 9
Device power dissipation (redriver mode) PD2 225 350 mW OE = H, HDMI_SEL = L, VCC = 3.3/3.6 V, VDD = 1.1/1.27 V, 3.4-Gbps TMDS pattern, VSadj = 6.5 kΩ 9
Device power with shut down PSD1 5 15 mW OE = L, VCC = 3.3/3.6 V, VDD = 1.1/1.27 V, VSadj = 7.06 kΩ 9
VDD supply current (TMDS 3.4-Gbps retimer mode) IDD1 250 300 mA OE = H, HDMI_SEL = L, VCC = 3.3/3.6 V, VDD = 1.1/1.27 V, 3.4-Gbps TMDS pattern, SLEW_CTL = H 9
VCC supply current (TMDS 3.4-Gbps retimer mode) ICC1 35 50 mA OE = H, HDMI_SEL = L, VCC = 3.3/3.6 V, VDD = 1.1/1.27 V, 3.4-Gbps TMDS pattern, SLEW_CTL = H 9
VDD supply current (TMDS 3.4-Gbps redriver mode) IDD2 170 200 mA OE = H, HDMI_SEL = L, VCC = 3.3/3.6 V, VDD = 1.1/1.27 V, 3.4-Gbps TMDS pattern, SLEW_CTL = H 9
VCC supply current (TMDS 3.4-Gbps redriver mode) ICC2 8 20 mA OE = H, HDMI_SEL = L, VCC = 3.3/3.6 V, VDD = 1.1/1.27 V, 3.4-Gbps TMDS pattern, SLEW_CTL = H 9
VDD shutdown current ISD1 3 10.5 mA OE = L, VCC = 3.3/3.6 V, VDD = 1.1/1.27 V, VSadj = 6.5 kΩ 9
VCC shutdown current ISD1 2 5 mA OE = L, VCC = 3.3/3.6 V, VDD = 1.1/1.27 V, VSadj = 6.5 kΩ 9
Ddata lanes data rate DR_RX_DATA 0.25 3.4 Gbps 10
Input differential termination impedance RINT 80 100 120 Ω 10
Input clock duty cycle tRX_DUTY 40 50 60 % 10
Single-ended high level output voltage (offset from VCC) VOH -10 10 mV Offset from VCC; data rate ≤ 1.65 Gbps; PRE_SEL = NC; SLEW_CTL = H; OE = H; DR = 750 Mbps; VSadj = 7.06 kΩ 11
Single-ended high level output voltage (offset from VCC) VOH -200 10 mV Offset from VCC; 1.65 Gbps < data rate ≤ 3.4 Gbps; PRE_SEL = NC; SLEW_CTL = H; OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ 11
Single-ended low level output voltage (offset from VCC) VOL -600 -400 mV Offset from VCC; data rate ≤ 1.65 Gbps; PRE_SEL = NC; SLEW_CTL = H; OE = H; DR = 750 Mbps; VSadj = 6.5 kΩ 11
Single-ended low level output voltage (offset from VCC) VOL -700 -400 mV Offset from VCC; 1.65-Gbps < data rate ≤ 3.4-Gbps; PRE_SEL = NC; SLEW_CTL = H; OE = H; DR = 2.97-Gbps; VSadj = 6.5 kΩ 11
Single-ended output voltage swing on data lane VSWING_DA 400 500 600 mV PRE_SEL = NC; SLEW_CTL = H; OE = H; DR = 270 Mbps/2.97 Gbps; VSadj = 6.5 kΩ 11
Single-ended output voltage swing on clock lane VSWING_CLK 400 500 600 mV Data rate ≤ 3.4 Gbps; PRE_SEL = NC; SLEW_CTL = H; OE = H; VSadj = 6.5 kΩ 11
Output differential voltage before pre-emphasis VOD(PP) 800 1200 mV VSadj = 7.06 kΩ; PRE_SEL = Z; see Figure 8 11
Steady-state output differential voltage VOD(SS) 600 1050 mV VSadj = 7.06 kΩ; PRE_SEL = L; see Figure 9 11
Source termination resistance for HDMI 2.0 RTERM 75 150 Ω 11
High-level input voltage HPD_SNK VIH 2.1 V HPD_SNK 12
Low-level input voltage HPD_SNK VIL 0.8 V HPD_SNK 12
High-level output voltage HPD_SRC VOH 2.4 3.6 V IOH = -50 µA; HPD_SRC 12
SCL/SDA_SNK high level input voltage VIH 3 V SCL/SDA_SNK 12
Supply voltage VDD (recommended) Vsadj 6.5 kΩ TMDS-compliant swing voltage bias resistor to GND; 1% precision recommended 8
Junction-to-ambient thermal resistance RθJA 37.3 °C/W 8
Junction-to-board thermal resistance RθJB 9.9 °C/W High-K board 8
Junction-to-case (top) thermal resistance RθJC(top) 23.1 °C/W High-K board 8
Junction-to-case (bottom) thermal resistance RθJC(bot) 3.2 °C/W 8
Junction-to-top characterization parameter ψJT 0.3 °C/W 8
Junction-to-case (bottom) characterization parameter ψJB 3.2 °C/W 8

CAD (KiCad official)

  • Symbol: SN75DP149RSBT
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: WQFN-40-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: sn75dp149rsbt-etched.step / sn75dp149rsbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn75dp149rsbt.step / sn75dp149rsbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (54 pp, sha256 9538c583822a0183, retrieved 2026-10-28, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF