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SN75DP130SSRGZR

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Texas Instruments Interface - Specialized, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN75DP130SSRGZR

Texas Instruments · Interface - Specialized · VQFN-48-EP(7x7)

SN75DP130SSRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in 3.3-V supply (recommended 3 V to 3.6 V).
2 VDDD_DREG passive Digital voltage regulator decoupling on the SS option; install 1 µF to GND.
3 ADDR_EQ input 3-level input that selects the I2C target address and configures the input EQ.
4 SCL_CTL bidirectional I2C clock of the interface that configures the SN75DP130; active independent of EN but inactive when RSTN is low.
5 SDA_CTL bidirectional I2C data of the interface that configures the SN75DP130; active independent of EN but inactive when RSTN is low.
6 VCC power_in 3.3-V supply (recommended 3 V to 3.6 V).
7 NC unconnected No connect; may be left unconnected or connected to GND.
8 CAD_SRC output DP cable adapter detect output, typically driving the GPU CAD input.
9 HPD_SRC output Hot Plug Detect output to the DisplayPort source.
10 CAD_SNK input DP cable adapter detect input that selects DP or TMDS mode; tolerates a 5-V supply with supply impedance above 90 kΩ, internal zener limits to 3.3 V, external 1 MΩ to GND recommended.
11 HPD_SNK input DisplayPort Hot Plug Detect input from the sink; 5-V tolerant.
12 VCC power_in 3.3-V supply (recommended 3 V to 3.6 V).
13 OUT3n output DisplayPort Main Link Lane 3 differential output, negative (100-Ω differential).
14 OUT3p output DisplayPort Main Link Lane 3 differential output, positive (100-Ω differential).
15 NC unconnected No connect on the SS option; may be left unconnected or connected to GND.
16 OUT2n output DisplayPort Main Link Lane 2 differential output, negative (100-Ω differential).
17 OUT2p output DisplayPort Main Link Lane 2 differential output, positive (100-Ω differential).
18 GND power_in Ground reference.
19 OUT1n output DisplayPort Main Link Lane 1 differential output, negative (100-Ω differential).
20 OUT1p output DisplayPort Main Link Lane 1 differential output, positive (100-Ω differential).
21 NC unconnected No connect on the SS option; may be left unconnected or connected to GND.
22 OUT0n output DisplayPort Main Link Lane 0 differential output, negative (100-Ω differential).
23 OUT0p output DisplayPort Main Link Lane 0 differential output, positive (100-Ω differential).
24 GND power_in Ground reference.
25 VCC power_in 3.3-V supply (recommended 3 V to 3.6 V).
26 EN input Device enable input with internal 200-kΩ pullup.
27 AUX_SNKn bidirectional Sink-side bidirectional DisplayPort auxiliary data channel, negative (100-Ω differential).
28 AUX_SNKp bidirectional Sink-side bidirectional DisplayPort auxiliary data channel, positive (100-Ω differential).
29 AUX_SRCn bidirectional Source-side bidirectional DisplayPort auxiliary data channel, negative; may be left open if AUX_SNK is used for monitoring only.
30 AUX_SRCp bidirectional Source-side bidirectional DisplayPort auxiliary data channel, positive; may be left open if AUX_SNK is used for monitoring only.
31 GND power_in Ground reference.
32 VCC power_in 3.3-V supply (recommended 3 V to 3.6 V).
33 SCL_DDC bidirectional I2C Display Data Channel clock for TMDS mode with integrated 60-kΩ pullup.
34 SDA_DDC bidirectional I2C Display Data Channel data for TMDS mode with integrated 60-kΩ pullup.
35 RSTN input Active-low device reset with 150-kΩ resistor to VDDD; asserting it enters Shutdown mode and resets all I2C and DPCD registers; must not be de-asserted until VCC and VDDD reach minimum levels.
36 VCC power_in 3.3-V supply (recommended 3 V to 3.6 V).
37 NC unconnected No connect on the SS option; may be left unconnected or connected to GND.
38 IN0p input DisplayPort Main Link Lane 0 differential input, positive (100-Ω differential).
39 IN0n input DisplayPort Main Link Lane 0 differential input, negative (100-Ω differential).
40 NC unconnected No connect; may be left unconnected or connected to GND.
41 IN1p input DisplayPort Main Link Lane 1 differential input, positive (100-Ω differential).
42 IN1n input DisplayPort Main Link Lane 1 differential input, negative (100-Ω differential).
43 NC unconnected No connect on the SS option; may be left unconnected or connected to GND.
44 IN2p input DisplayPort Main Link Lane 2 differential input, positive (100-Ω differential).
45 IN2n input DisplayPort Main Link Lane 2 differential input, negative (100-Ω differential).
46 NC unconnected No connect; may be left unconnected or connected to GND.
47 IN3p input DisplayPort Main Link Lane 3 differential input, positive (100-Ω differential).
48 IN3n input DisplayPort Main Link Lane 3 differential input, negative (100-Ω differential).
49 GND power_in Exposed thermal pad; ground reference connection, with several GND vias recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: SN75DP130SSRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: sn75dp130ssrgzr-etched.step / sn75dp130ssrgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn75dp130ssrgzr.step / sn75dp130ssrgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (55 pp, sha256 582604cddc669284, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF