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SN75DP130DSRGZR

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Texas Instruments Video Interface ICs, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN75DP130DSRGZR

Texas Instruments · Video Interface ICs · VQFN-48-EP(7x7)

SN75DP130DSRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in 3.3-V supply for the DS option (3.0 V to 3.6 V recommended); pin 36 is also VCC.
2 VDDD_DREG power_in For the DS option, treat as VDDD; this pin is the noisiest of all VDDD terminals and needs a decoupling capacitor nearby.
3 ADDR_EQ input 3-level input that selects the I2C target address and the input EQ configuration (see Table 3).
4 SCL_CTL bidirectional Local I2C interface clock to configure the SN75DP130; active independent of EN but inactive when RSTN is low.
5 SDA_CTL bidirectional Local I2C interface data to configure the SN75DP130; active independent of EN but inactive when RSTN is low.
6 VDDD power_in Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V).
7 NC unconnected No connect; may be left unconnected or connected to GND.
8 CAD_SRC output DisplayPort cable adapter detect output that typically drives the GPU CAD input.
9 HPD_SRC output Hot plug detect output to the DisplayPort source.
10 CAD_SNK input DisplayPort cable adapter detect input that tolerates a 5-V supply with supply impedance above 90 kΩ, with an internal zener limiting the input to 3.3 V; an external 1 MΩ resistor to GND is recommended.
11 HPD_SNK input DisplayPort hot plug detect input from the sink, which is 5-V tolerant; pull high for compliance testing or use I2C to enter compliance test mode.
12 VDDD power_in Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V).
13 OUT3n output DisplayPort Main Link lane 3 differential output (100-Ω differential), with output termination of 80 to 120 Ω.
14 OUT3p output DisplayPort Main Link lane 3 differential output (100-Ω differential), with output termination of 80 to 120 Ω.
15 VDDD power_in Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V).
16 OUT2n output DisplayPort Main Link lane 2 differential output (100-Ω differential), with output termination of 80 to 120 Ω.
17 OUT2p output DisplayPort Main Link lane 2 differential output (100-Ω differential), with output termination of 80 to 120 Ω.
18 GND power_in Ground reference connection, including through the device exposed thermal pad.
19 OUT1n output DisplayPort Main Link lane 1 differential output (100-Ω differential), with output termination of 80 to 120 Ω.
20 OUT1p output DisplayPort Main Link lane 1 differential output (100-Ω differential), with output termination of 80 to 120 Ω.
21 VDDD power_in Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V).
22 OUT0n output DisplayPort Main Link lane 0 differential output (100-Ω differential), with output termination of 80 to 120 Ω.
23 OUT0p output DisplayPort Main Link lane 0 differential output (100-Ω differential), with output termination of 80 to 120 Ω.
24 GND power_in Ground reference connection, including through the device exposed thermal pad.
25 VDDD power_in Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V).
26 EN input Device enable input with an internal 200-kΩ pullup.
27 AUX_SNKn bidirectional Sink-side bidirectional DisplayPort auxiliary data channel (100-Ω differential); AC coupling capacitors are used on this channel.
28 AUX_SNKp bidirectional Sink-side bidirectional DisplayPort auxiliary data channel (100-Ω differential); AC coupling capacitors are used on this channel.
29 AUX_SRCn bidirectional Source-side bidirectional DisplayPort auxiliary data channel (100-Ω differential); may be left open if AUX_SNK is used for monitoring only.
30 AUX_SRCp bidirectional Source-side bidirectional DisplayPort auxiliary data channel (100-Ω differential); may be left open if AUX_SNK is used for monitoring only.
31 GND power_in Ground reference connection, including through the device exposed thermal pad.
32 VDDD power_in Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V).
33 SCL_DDC bidirectional I2C display data channel clock for TMDS mode, with an integrated 60-kΩ pullup resistor.
34 SDA_DDC bidirectional I2C display data channel data for TMDS mode, with an integrated 60-kΩ pullup resistor.
35 RSTN input Active-low device reset with an internal 150-kΩ resistor to VDDD; asserting it puts outputs high-impedance and resets I2C and DPCD registers, and it must not be released until VCC and VDDD reach minimum recommended levels.
36 VCC power_in 3.3-V supply (3.0 V to 3.6 V recommended).
37 VDDD power_in Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V).
38 IN0p input DisplayPort Main Link lane 0 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps.
39 IN0n input DisplayPort Main Link lane 0 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps.
40 NC unconnected No connect; may be left unconnected or connected to GND.
41 IN1p input DisplayPort Main Link lane 1 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps.
42 IN1n input DisplayPort Main Link lane 1 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps.
43 VDDD power_in Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V).
44 IN2p input DisplayPort Main Link lane 2 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps.
45 IN2n input DisplayPort Main Link lane 2 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps.
46 NC unconnected No connect; may be left unconnected or connected to GND.
47 IN3p input DisplayPort Main Link lane 3 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps.
48 IN3n input DisplayPort Main Link lane 3 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: SN75DP130DSRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: sn75dp130dsrgzr-etched.step / sn75dp130dsrgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn75dp130dsrgzr.step / sn75dp130dsrgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (55 pp, sha256 582604cddc669284, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF