component
SN75DP130DSRGZR
Public Made by Adomby adom
Texas Instruments Video Interface ICs, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+86@@ -0,0 +1,86 @@+# SN75DP130DSRGZR++**Texas Instruments** · Video Interface ICs · VQFN-48-EP(7x7)++SN75DP130DSRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VCC | power_in | 3.3-V supply for the DS option (3.0 V to 3.6 V recommended); pin 36 is also VCC. |+| 2 | VDDD_DREG | power_in | For the DS option, treat as VDDD; this pin is the noisiest of all VDDD terminals and needs a decoupling capacitor nearby. |+| 3 | ADDR_EQ | input | 3-level input that selects the I2C target address and the input EQ configuration (see Table 3). |+| 4 | SCL_CTL | bidirectional | Local I2C interface clock to configure the SN75DP130; active independent of EN but inactive when RSTN is low. |+| 5 | SDA_CTL | bidirectional | Local I2C interface data to configure the SN75DP130; active independent of EN but inactive when RSTN is low. |+| 6 | VDDD | power_in | Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V). |+| 7 | NC | unconnected | No connect; may be left unconnected or connected to GND. |+| 8 | CAD_SRC | output | DisplayPort cable adapter detect output that typically drives the GPU CAD input. |+| 9 | HPD_SRC | output | Hot plug detect output to the DisplayPort source. |+| 10 | CAD_SNK | input | DisplayPort cable adapter detect input that tolerates a 5-V supply with supply impedance above 90 kΩ, with an internal zener limiting the input to 3.3 V; an external 1 MΩ resistor to GND is recommended. |+| 11 | HPD_SNK | input | DisplayPort hot plug detect input from the sink, which is 5-V tolerant; pull high for compliance testing or use I2C to enter compliance test mode. |+| 12 | VDDD | power_in | Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V). |+| 13 | OUT3n | output | DisplayPort Main Link lane 3 differential output (100-Ω differential), with output termination of 80 to 120 Ω. |+| 14 | OUT3p | output | DisplayPort Main Link lane 3 differential output (100-Ω differential), with output termination of 80 to 120 Ω. |+| 15 | VDDD | power_in | Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V). |+| 16 | OUT2n | output | DisplayPort Main Link lane 2 differential output (100-Ω differential), with output termination of 80 to 120 Ω. |+| 17 | OUT2p | output | DisplayPort Main Link lane 2 differential output (100-Ω differential), with output termination of 80 to 120 Ω. |+| 18 | GND | power_in | Ground reference connection, including through the device exposed thermal pad. |+| 19 | OUT1n | output | DisplayPort Main Link lane 1 differential output (100-Ω differential), with output termination of 80 to 120 Ω. |+| 20 | OUT1p | output | DisplayPort Main Link lane 1 differential output (100-Ω differential), with output termination of 80 to 120 Ω. |+| 21 | VDDD | power_in | Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V). |+| 22 | OUT0n | output | DisplayPort Main Link lane 0 differential output (100-Ω differential), with output termination of 80 to 120 Ω. |+| 23 | OUT0p | output | DisplayPort Main Link lane 0 differential output (100-Ω differential), with output termination of 80 to 120 Ω. |+| 24 | GND | power_in | Ground reference connection, including through the device exposed thermal pad. |+| 25 | VDDD | power_in | Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V). |+| 26 | EN | input | Device enable input with an internal 200-kΩ pullup. |+| 27 | AUX_SNKn | bidirectional | Sink-side bidirectional DisplayPort auxiliary data channel (100-Ω differential); AC coupling capacitors are used on this channel. |+| 28 | AUX_SNKp | bidirectional | Sink-side bidirectional DisplayPort auxiliary data channel (100-Ω differential); AC coupling capacitors are used on this channel. |+| 29 | AUX_SRCn | bidirectional | Source-side bidirectional DisplayPort auxiliary data channel (100-Ω differential); may be left open if AUX_SNK is used for monitoring only. |+| 30 | AUX_SRCp | bidirectional | Source-side bidirectional DisplayPort auxiliary data channel (100-Ω differential); may be left open if AUX_SNK is used for monitoring only. |+| 31 | GND | power_in | Ground reference connection, including through the device exposed thermal pad. |+| 32 | VDDD | power_in | Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V). |+| 33 | SCL_DDC | bidirectional | I2C display data channel clock for TMDS mode, with an integrated 60-kΩ pullup resistor. |+| 34 | SDA_DDC | bidirectional | I2C display data channel data for TMDS mode, with an integrated 60-kΩ pullup resistor. |+| 35 | RSTN | input | Active-low device reset with an internal 150-kΩ resistor to VDDD; asserting it puts outputs high-impedance and resets I2C and DPCD registers, and it must not be released until VCC and VDDD reach minimum recommended levels. |+| 36 | VCC | power_in | 3.3-V supply (3.0 V to 3.6 V recommended). |+| 37 | VDDD | power_in | Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V). |+| 38 | IN0p | input | DisplayPort Main Link lane 0 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps. |+| 39 | IN0n | input | DisplayPort Main Link lane 0 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps. |+| 40 | NC | unconnected | No connect; may be left unconnected or connected to GND. |+| 41 | IN1p | input | DisplayPort Main Link lane 1 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps. |+| 42 | IN1n | input | DisplayPort Main Link lane 1 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps. |+| 43 | VDDD | power_in | Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V). |+| 44 | IN2p | input | DisplayPort Main Link lane 2 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps. |+| 45 | IN2n | input | DisplayPort Main Link lane 2 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps. |+| 46 | NC | unconnected | No connect; may be left unconnected or connected to GND. |+| 47 | IN3p | input | DisplayPort Main Link lane 3 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps. |+| 48 | IN3n | input | DisplayPort Main Link lane 3 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Interface |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `SN75DP130DSRGZR`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `sn75dp130dsrgzr-etched.step` / `sn75dp130dsrgzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn75dp130dsrgzr.step` / `sn75dp130dsrgzr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn75dp130) (55 pp, sha256 `582604cddc669284`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn75dp130dsrgzr-datasheet.pdf)
page.jsonadded+446@@ -0,0 +1,446 @@+{+ "slug": "sn75dp130dsrgzr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Video Interface ICs, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "sn75dp130dsrgzr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn75dp130dsrgzr.kicad_sym",+ "sn75dp130dsrgzr.kicad_mod",+ "sn75dp130dsrgzr.glb",+ "sn75dp130dsrgzr.step",+ "sn75dp130dsrgzr.lbr",+ "docs/hero.png",+ "docs/sn75dp130dsrgzr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn75dp130dsrgzr-hero.glb",+ "sn75dp130dsrgzr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN75DP130DSRGZR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "Interface",+ "subcategory": "Video Interface ICs",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn75dp130",+ "parts": {+ "symbol": "sn75dp130dsrgzr.kicad_sym",+ "footprint": "sn75dp130dsrgzr.kicad_mod",+ "model_3d": "sn75dp130dsrgzr-hero.glb",+ "model_3d_plain": "sn75dp130dsrgzr.glb",+ "model_3d_step": "sn75dp130dsrgzr-etched.step",+ "model_3d_step_plain": "sn75dp130dsrgzr.step",+ "lbr": "sn75dp130dsrgzr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2676823",+ "digikey": "296-28739-2-ND"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T20:56:35Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-28739-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": null,+ "status": "error"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VCC",+ "type": "power_in",+ "description": "3.3-V supply for the DS option (3.0 V to 3.6 V recommended); pin 36 is also VCC."+ },+ {+ "number": "2",+ "name": "VDDD_DREG",+ "type": "power_in",+ "description": "For the DS option, treat as VDDD; this pin is the noisiest of all VDDD terminals and needs a decoupling capacitor nearby."+ },+ {+ "number": "3",+ "name": "ADDR_EQ",+ "type": "input",+ "description": "3-level input that selects the I2C target address and the input EQ configuration (see Table 3)."+ },+ {+ "number": "4",+ "name": "SCL_CTL",+ "type": "bidirectional",+ "description": "Local I2C interface clock to configure the SN75DP130; active independent of EN but inactive when RSTN is low."+ },+ {+ "number": "5",+ "name": "SDA_CTL",+ "type": "bidirectional",+ "description": "Local I2C interface data to configure the SN75DP130; active independent of EN but inactive when RSTN is low."+ },+ {+ "number": "6",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V)."+ },+ {+ "number": "7",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect; may be left unconnected or connected to GND."+ },+ {+ "number": "8",+ "name": "CAD_SRC",+ "type": "output",+ "description": "DisplayPort cable adapter detect output that typically drives the GPU CAD input."+ },+ {+ "number": "9",+ "name": "HPD_SRC",+ "type": "output",+ "description": "Hot plug detect output to the DisplayPort source."+ },+ {+ "number": "10",+ "name": "CAD_SNK",+ "type": "input",+ "description": "DisplayPort cable adapter detect input that tolerates a 5-V supply with supply impedance above 90 kΩ, with an internal zener limiting the input to 3.3 V; an external 1 MΩ resistor to GND is recommended."+ },+ {+ "number": "11",+ "name": "HPD_SNK",+ "type": "input",+ "description": "DisplayPort hot plug detect input from the sink, which is 5-V tolerant; pull high for compliance testing or use I2C to enter compliance test mode."+ },+ {+ "number": "12",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V)."+ },+ {+ "number": "13",+ "name": "OUT3n",+ "type": "output",+ "description": "DisplayPort Main Link lane 3 differential output (100-Ω differential), with output termination of 80 to 120 Ω."+ },+ {+ "number": "14",+ "name": "OUT3p",+ "type": "output",+ "description": "DisplayPort Main Link lane 3 differential output (100-Ω differential), with output termination of 80 to 120 Ω."+ },+ {+ "number": "15",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V)."+ },+ {+ "number": "16",+ "name": "OUT2n",+ "type": "output",+ "description": "DisplayPort Main Link lane 2 differential output (100-Ω differential), with output termination of 80 to 120 Ω."+ },+ {+ "number": "17",+ "name": "OUT2p",+ "type": "output",+ "description": "DisplayPort Main Link lane 2 differential output (100-Ω differential), with output termination of 80 to 120 Ω."+ },+ {+ "number": "18",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference connection, including through the device exposed thermal pad."+ },+ {+ "number": "19",+ "name": "OUT1n",+ "type": "output",+ "description": "DisplayPort Main Link lane 1 differential output (100-Ω differential), with output termination of 80 to 120 Ω."+ },+ {+ "number": "20",+ "name": "OUT1p",+ "type": "output",+ "description": "DisplayPort Main Link lane 1 differential output (100-Ω differential), with output termination of 80 to 120 Ω."+ },+ {+ "number": "21",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V)."+ },+ {+ "number": "22",+ "name": "OUT0n",+ "type": "output",+ "description": "DisplayPort Main Link lane 0 differential output (100-Ω differential), with output termination of 80 to 120 Ω."+ },+ {+ "number": "23",+ "name": "OUT0p",+ "type": "output",+ "description": "DisplayPort Main Link lane 0 differential output (100-Ω differential), with output termination of 80 to 120 Ω."+ },+ {+ "number": "24",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference connection, including through the device exposed thermal pad."+ },+ {+ "number": "25",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V)."+ },+ {+ "number": "26",+ "name": "EN",+ "type": "input",+ "description": "Device enable input with an internal 200-kΩ pullup."+ },+ {+ "number": "27",+ "name": "AUX_SNKn",+ "type": "bidirectional",+ "description": "Sink-side bidirectional DisplayPort auxiliary data channel (100-Ω differential); AC coupling capacitors are used on this channel."+ },+ {+ "number": "28",+ "name": "AUX_SNKp",+ "type": "bidirectional",+ "description": "Sink-side bidirectional DisplayPort auxiliary data channel (100-Ω differential); AC coupling capacitors are used on this channel."+ },+ {+ "number": "29",+ "name": "AUX_SRCn",+ "type": "bidirectional",+ "description": "Source-side bidirectional DisplayPort auxiliary data channel (100-Ω differential); may be left open if AUX_SNK is used for monitoring only."+ },+ {+ "number": "30",+ "name": "AUX_SRCp",+ "type": "bidirectional",+ "description": "Source-side bidirectional DisplayPort auxiliary data channel (100-Ω differential); may be left open if AUX_SNK is used for monitoring only."+ },+ {+ "number": "31",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference connection, including through the device exposed thermal pad."+ },+ {+ "number": "32",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V)."+ },+ {+ "number": "33",+ "name": "SCL_DDC",+ "type": "bidirectional",+ "description": "I2C display data channel clock for TMDS mode, with an integrated 60-kΩ pullup resistor."+ },+ {+ "number": "34",+ "name": "SDA_DDC",+ "type": "bidirectional",+ "description": "I2C display data channel data for TMDS mode, with an integrated 60-kΩ pullup resistor."+ },+ {+ "number": "35",+ "name": "RSTN",+ "type": "input",+ "description": "Active-low device reset with an internal 150-kΩ resistor to VDDD; asserting it puts outputs high-impedance and resets I2C and DPCD registers, and it must not be released until VCC and VDDD reach minimum recommended levels."+ },+ {+ "number": "36",+ "name": "VCC",+ "type": "power_in",+ "description": "3.3-V supply (3.0 V to 3.6 V recommended)."+ },+ {+ "number": "37",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V)."+ },+ {+ "number": "38",+ "name": "IN0p",+ "type": "input",+ "description": "DisplayPort Main Link lane 0 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps."+ },+ {+ "number": "39",+ "name": "IN0n",+ "type": "input",+ "description": "DisplayPort Main Link lane 0 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps."+ },+ {+ "number": "40",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect; may be left unconnected or connected to GND."+ },+ {+ "number": "41",+ "name": "IN1p",+ "type": "input",+ "description": "DisplayPort Main Link lane 1 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps."+ },+ {+ "number": "42",+ "name": "IN1n",+ "type": "input",+ "description": "DisplayPort Main Link lane 1 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps."+ },+ {+ "number": "43",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital low-voltage core and Main Link supply, nominally 1.1 V (recommended 0.97 V to 1.2 V)."+ },+ {+ "number": "44",+ "name": "IN2p",+ "type": "input",+ "description": "DisplayPort Main Link lane 2 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps."+ },+ {+ "number": "45",+ "name": "IN2n",+ "type": "input",+ "description": "DisplayPort Main Link lane 2 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps."+ },+ {+ "number": "46",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect; may be left unconnected or connected to GND."+ },+ {+ "number": "47",+ "name": "IN3p",+ "type": "input",+ "description": "DisplayPort Main Link lane 3 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps."+ },+ {+ "number": "48",+ "name": "IN3n",+ "type": "input",+ "description": "DisplayPort Main Link lane 3 differential input (100-Ω differential), specified for 0.3 to 1.40 Vpp input differential voltage at up to 5.4 Gbps."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed thermal pad is listed as GND ('Exposed Thermal Pad') but the datasheet gives it no pin n; Pin assignments are for the DS (dual-supply) option, matching the MPN SN75DP130DSRGZR (ordering adde; The VDDD/VCC/VDDD_DREG supply assignments were taken from the supply table on page 6 because the pag",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 17,+ "cost_usd": 0.1382,+ "at": "2026-10-08T20:56:17"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn75dp130",+ "pages": 55,+ "sha256": "582604cddc669284",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn75dp130dsrgzr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn75dp130dsrgzr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "6a10135a77624c63f01dc7c082b042143c6b10d21b4f825d4e71e9d2c28c02f8",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}