component
SN75374N
Public Made by Adomby adom
Texas Instruments Pre-ordered Chips, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 10d ago |
| viewers | 10d ago |
| package.json | 10d ago |
| page.json | 10d ago |
| README.md | 10d ago |
| sn75374n-etched.glb | 10d ago |
| sn75374n-etched.step | 10d ago |
| sn75374n-hero.glb | 10d ago |
| sn75374n-hero.overlay.json | 10d ago |
| sn75374n.glb | 10d ago |
| sn75374n.kicad_mod | 10d ago |
| sn75374n.kicad_sym | 10d ago |
| sn75374n.lbr | 10d ago |
| sn75374n.step | 10d ago |
| verification.json | 10d ago |
SN75374N
Texas Instruments · Pre-ordered Chips · PDIP-16
SN75374N from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC2 | power_in | Output stage supply, 4.75 V to 24 V recommended (20 V nominal), absolute maximum 25 V; outputs switch close to this rail. |
| 2 | 1Y | output | Totem-pole output of driver 1, rated for 40 mA low-level and −10 mA high-level output current. |
| 3 | 1A | input | Driver 1 TTL logic input, high level at least 2 V, low level at most 0.8 V, maximum 5.5 V. |
| 4 | 1E1 | input | Driver 1 enable input E1, TTL levels (NAND function with A and E2), maximum 5.5 V. |
| 5 | 1E2 | input | Driver 1 enable input E2, TTL levels (NAND function with A and E1), maximum 5.5 V. |
| 6 | 2A | input | Driver 2 TTL logic input, high level at least 2 V, low level at most 0.8 V, maximum 5.5 V. |
| 7 | 2Y | output | Totem-pole output of driver 2, rated for 40 mA low-level and −10 mA high-level output current. |
| 8 | GND | power_in | Ground, reference terminal for all supply voltages. |
| 9 | VCC3 | power_in | Pull-up boost supply, 28 V maximum recommended (absolute max 30 V), about 3 V above VCC2 to maximize output source voltage, or tied to VCC2. |
| 10 | 3Y | output | Totem-pole output of driver 3, rated for 40 mA low-level and −10 mA high-level output current. |
| 11 | 3A | input | Driver 3 TTL logic input, high level at least 2 V, low level at most 0.8 V, maximum 5.5 V. |
| 12 | 2E1 | input | Driver 2 enable input E1, TTL levels (NAND function with A and E2), maximum 5.5 V. |
| 13 | 2E2 | input | Driver 2 enable input E2, TTL levels (NAND function with A and E1), maximum 5.5 V. |
| 14 | 4A | input | Driver 4 TTL logic input, high level at least 2 V, low level at most 0.8 V, maximum 5.5 V. |
| 15 | 4Y | output | Totem-pole output of driver 4, rated for 40 mA low-level and −10 mA high-level output current. |
| 16 | VCC1 | power_in | Logic supply, 4.75 V to 5.25 V recommended (5 V nominal), absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-16 |
| Category | Interface ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input clamp voltage | VIK | -1.5 | V | II = −12 mA | 3 | ||
| Low-level output voltage | VOL | 0.15 | 0.3 | V | VIH = 2 V, IOL = 10 mA | 3 | |
| Low-level output voltage | VOL | 0.25 | 0.5 | V | VCC2 = 15 V to 28 V, VIH = 2 V, IOL = 40 mA | 3 | |
| Output clamp-diode forward voltage | VF | 1.5 | V | VI = 0, IF = 20 mA | 3 | ||
| Input current at maximum input voltage | II | 1 | mA | VI = 5.5 V | 3 | ||
| High-level input current, Any A | IIH | 40 | µA | VI = 2.4 V | 3 | ||
| High-level input current, Any E | IIH | 80 | µA | VI = 2.4 V | 3 | ||
| Low-level input current, Any A | IIL | -1 | -1.6 | mA | VI = 0.4 V | 3 | |
| Low-level input current, Any E | IIL | -2 | -3.2 | mA | VI = 0.4 V | 3 | |
| Supply current from VCC1, all outputs high | ICC1(H) | 4 | 8 | mA | All outputs high | 3 | |
| Supply current from VCC1, all outputs low | ICC1(L) | 31 | 47 | mA | All outputs low | 3 | |
| Supply current from VCC2, all outputs high | ICC2(H) | -2.2 | 0.25 | mA | VCC1 = 5.25 V, All inputs at 0 V, VCC2 = 24 V, VCC3 = 28 V, No load | 3 | |
| Supply current from VCC2, all outputs low | ICC2(L) | 2 | mA | VCC1 = 5.25 V, All inputs at 5 V, VCC2 = 24 V, VCC3 = 28 V, No load | 3 | ||
| Supply current from VCC3, all outputs high | ICC3(H) | 2.2 | 3.5 | mA | All inputs at 0 V, No load | 3 | |
| Supply current from VCC3, all outputs low | ICC3(L) | 16 | 27 | mA | All inputs at 5 V, No load | 3 | |
| Supply current from VCC2, all outputs high (VCC3 = 24 V) | ICC2(H) | 0.25 | mA | VCC1 = 5.25 V, All inputs at 0 V, VCC2 = 24 V, VCC3 = 24 V, No load | 3 | ||
| Supply current from VCC3, all outputs high (VCC3 = 24 V) | ICC3(H) | 0.5 | mA | VCC1 = 5.25 V, All inputs at 0 V, VCC2 = 24 V, VCC3 = 24 V, No load | 3 | ||
| Supply current from VCC2, standby condition | ICC2(S) | 0.25 | mA | VCC1 = 0, VCC2 = 24 V, VCC3 = 24 V | 3 | ||
| Supply current from VCC3, standby condition | ICC3(S) | 0.5 | mA | VCC1 = 0, All inputs at 0 V, VCC2 = 24 V, VCC3 = 24 V, No load | 3 | ||
| Delay time, low- to high-level output | tDLH | 20 | 30 | ns | C = 200 pF; VCC1 = 5 V, VCC2 = 20 V, VCC3 = 24 V, TA = 25°C | 3 | |
| Delay time, high- to low-level output | tDHL | 10 | 20 | ns | C = 200 pF; VCC1 = 5 V, VCC2 = 20 V, VCC3 = 24 V, TA = 25°C | 3 | |
| Propagation delay time, low- to high-level output | tPLH | 10 | 40 | 60 | ns | CL = 200 pF, RD = 24 Ω; VCC1 = 5 V, VCC2 = 20 V, VCC3 = 24 V, TA = 25°C | 3 |
| Propagation delay time, high- to low-level output | tPHL | 10 | 30 | 50 | ns | RD = 24 Ω, See Figure 1; VCC1 = 5 V, VCC2 = 20 V, VCC3 = 24 V, TA = 25°C | 3 |
| Transition time, low- to high-level output | tTLH | 20 | 30 | ns | See Figure 1; VCC1 = 5 V, VCC2 = 20 V, VCC3 = 24 V, TA = 25°C | 3 | |
| Transition time, high- to low-level output | tTHL | 20 | 30 | ns | See Figure 1; VCC1 = 5 V, VCC2 = 20 V, VCC3 = 24 V, TA = 25°C | 3 | |
| Supply voltage VCC1 | VCC1 | 4.75 | 5 | 5.25 | V | 2 | |
| Supply voltage VCC2 | VCC2 | 4.75 | 20 | 24 | V | 2 | |
| Supply voltage VCC3 | VCC3 | 24 | 28 | V | 2 | ||
| Voltage difference between supply voltages | VCC3 − VCC2 | 0 | 4 | 10 | V | 2 | |
| High-level input voltage | VIH | 2 | V | 2 | |||
| Low-level input voltage | VIL | 0.8 | V | 2 | |||
| High-level output current | IOH | -10 | mA | 2 | |||
| Low-level output current | IOL | 40 | mA | 2 | |||
| Operating free-air temperature | TA | 0 | 70 | °C | 2 | ||
| Supply voltage range VCC1 | VCC1 | -0.5 | 7 | V | Voltage with respect to network ground terminal | 2 | |
| Supply voltage range VCC2 | VCC2 | -0.5 | 25 | V | Voltage with respect to network ground terminal | 2 | |
| Supply voltage range VCC3 | VCC3 | -0.5 | 30 | V | Voltage with respect to network ground terminal | 2 | |
| Input voltage | VI | 5.5 | V | 2 | |||
| Peak output current | II | 500 | mA | tw < 10 ms, duty cycle < 50% | 2 | ||
| Package thermal impedance, N package | θJA | 67 | °C/W | N package, see Notes 2 and 3 | 2 | ||
| Operating virtual junction temperature | TJ | 150 | °C | 2 | |||
| Storage temperature range | Tstg | -65 | 150 | °C | 2 |
CAD (KiCad official)
- Symbol:
SN75374N - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: PDIP-16 (KiCad packages3D, STEP)
- 3D model files:
sn75374n-etched.step/sn75374n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn75374n.step/sn75374n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (19 pp, sha256
89a79d6677da2e65, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).