component
SN75182N
Public Made by Adomby adom
Texas Instruments Interface - Specialized, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN75182N
Texas Instruments · Interface - Specialized · PDIP-14
SN75182N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1IN- | input | Inverting input of receiver 1, with a common-mode input range of ±15 V and a differential input voltage range of ±15 V, and an input resistance of 3.6 kΩ minimum. |
| 2 | 1RT | passive | Optional built-in line-termination resistor terminal for receiver 1, with a line-terminating resistance of 120 Ω minimum, 170 Ω typical and 250 Ω maximum at TA = 25°C. |
| 3 | 1IN+ | input | Noninverting input of receiver 1, with an input resistance of 1.8 kΩ minimum and 2.5 kΩ typical. |
| 4 | 1STRB | input | Channel 1 strobe input, where a low level (0 V to 0.9 V) disables the receiver and forces the output high, and a high level (2.1 V to 5.5 V) or open enables it. |
| 5 | 1RTC | passive | Response-time control terminal for receiver 1, where an optional external capacitor sets the frequency response and noise-pulse immunity. |
| 6 | 1OUT | output | TTL-compatible output of receiver 1, which goes high when the inputs are open circuited and can sink up to 16 mA at low level. |
| 7 | GND | power_in | Network ground terminal shared by both receiver halves. |
| 8 | 2OUT | output | TTL-compatible output of receiver 2, which goes high when the inputs are open circuited and can sink up to 16 mA at low level. |
| 9 | 2RTC | passive | Response-time control terminal for receiver 2, where an optional external capacitor sets the frequency response and noise-pulse immunity. |
| 10 | 2STRB | input | Channel 2 strobe input, where a low level (0 V to 0.9 V) disables the receiver and forces the output high, and a high level (2.1 V to 5.5 V) or open enables it. |
| 11 | 2IN+ | input | Noninverting input of receiver 2, with an input resistance of 1.8 kΩ minimum and 2.5 kΩ typical. |
| 12 | 2RT | passive | Optional built-in line-termination resistor terminal for receiver 2, with a line-terminating resistance of 120 Ω minimum, 170 Ω typical and 250 Ω maximum at TA = 25°C. |
| 13 | 2IN- | input | Inverting input of receiver 2, with a common-mode input range of ±15 V and a differential input voltage range of ±15 V, and an input resistance of 3.6 kΩ minimum. |
| 14 | VCC | power_in | Single 5-V supply input, with a recommended supply voltage of 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| Common-mode input voltage | VIC | -15 | 15 | V | 4 | ||
| High-level strobe input voltage | VIH(STRB) | 2.1 | 5.5 | V | 4 | ||
| Low-level strobe input voltage | VIL(STRB) | 0 | 0.9 | V | 4 | ||
| High-level output current | IOH | -400 | µA | 4 | |||
| Low-level output current | IOL | 16 | mA | 4 | |||
| Operating free-air temperature | TA | 0 | 70 | °C | SN75182 | 4 | |
| Supply voltage | VCC | 8 | V | see Note 1 | 4 | ||
| Common-mode input voltage | VIC | -20 | 20 | V | 4 | ||
| Differential input voltage | VID | -20 | 20 | V | see Note 2 | 4 | |
| Strobe input voltage | VI(STRB) | 8 | V | 4 | |||
| Output sink current | 50 | mA | 4 | ||||
| Storage temperature range | Tstg | -65 | 150 | °C | 4 | ||
| Lead temperature, N package | 260 | °C | 1,6 mm from case for 10 seconds | 4 | |||
| Continuous total power dissipation, N package | 1150 | mW | TA <= 25°C; derating 9.2 mW/°C above TA = 25°C | 4 | |||
| Positive-going input threshold voltage | VIT+ | 0.5 | V | VO = 2.5 V, VIC = -3 V to 3 V | 5 | ||
| Positive-going input threshold voltage | VIT+ | 1 | V | VO = 2.5 V, IOH = -400 µA, VIC = -15 V to 15 V | 5 | ||
| Negative-going input threshold voltage | VIT- | -0.5 | V | VO = 0.4 V, VIC = -3 V to 3 V | 5 | ||
| Negative-going input threshold voltage | VIT- | -1 | V | VO = 0.4 V, IOL = 16 mA, VIC = -15 V to 15 V | 5 | ||
| High-level output voltage | VOH | 2.5 | 4.2 | 5.5 | V | VID = 1 V, V(STRB) = 2.1 V, IOH = -400 µA | 5 |
| Inverting input current | II | 3 | 4.2 | mA | VIC = 15 V | 5 | |
| Inverting input current | II | 0 | -0.5 | mA | VIC = 0 | 5 | |
| Inverting input current | II | -3 | -4.2 | mA | VIC = -15 V | 5 | |
| Noninverting input current | II | 5 | 7 | mA | VIC = 15 V | 5 | |
| Noninverting input current | II | -1 | -1.4 | mA | VIC = 0 | 5 | |
| Noninverting input current | II | -7 | -9.8 | mA | VIC = -15 V | 5 | |
| High-level strobe input current | IIH(STRB) | 5 | µA | V(STRB) = 5.5 V | 5 | ||
| Low-level strobe input current | IIL(STRB) | -1 | -1.4 | mA | V(STRB) = 0 | 5 | |
| Input resistance, inverting input | ri | 3.6 | 5 | kΩ | inverting input | 5 | |
| Input resistance, noninverting input | ri | 1.8 | 2.5 | kΩ | noninverting input | 5 | |
| Line-terminating resistance | 120 | 170 | 250 | Ω | TA = 25°C | 5 | |
| Short-circuit output current | IOS | -2.8 | -4.5 | -6.7 | mA | VCC = 5.5 V, VO = 0 | 5 |
| Supply current (average per receiver) | ICC | 4.2 | 6 | mA | VIC = 15 V, VID = -1 V | 5 | |
| Supply current (average per receiver) | ICC | 6.8 | 10.2 | mA | VIC = 0, VID = -0.5 V | 5 | |
| Supply current (average per receiver) | ICC | 9.4 | 14 | mA | VIC = -15 V, VID = -1 V | 5 | |
| Propagation delay time, low- to high-level output from differential input | tPLH(D) | 18 | 40 | ns | RL = 400 Ω, CL = 15 pF, see Figure 1 | 5 | |
| Propagation delay time, high- to low-level output from differential input | tPHL(D) | 31 | 45 | ns | RL = 400 Ω, CL = 15 pF, see Figure 1 | 5 | |
| Propagation delay time, low- to high-level output from STRB input | tPLH(S) | 9 | 30 | ns | RL = 400 Ω, CL = 15 pF, see Figure 1 | 5 | |
| Propagation delay time, high- to low-level output from STRB input | tPHL(S) | 15 | 25 | ns | RL = 400 Ω, CL = 15 pF, see Figure 1 | 5 |
CAD (KiCad official)
- Symbol:
SN75182N - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
sn75182n-etched.step/sn75182n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn75182n.step/sn75182n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
f21743865b181d3a, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).