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SN75176BD

Public Made by Adom

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Texas Instruments RS-485/RS-422 ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN75176BD

Texas Instruments · RS-485/RS-422 ICs · SOIC-8

SN75176BD from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 R output Logic data output from the RS-485 receiver; 3-state, high impedance when RE is high, with VOL max 0.45 V at 8 mA and VOH min 2.7 V at -400 µA.
2 RE input Receive enable, active low; high-level input voltage min 2 V and low-level max 0.8 V, and can be tied to DE for direction control.
3 DE input Driver enable, active high; high-level input voltage min 2 V and low-level max 0.8 V, and can be tied to RE for direction control.
4 D input Logic data input to the RS-485 driver; high-level input voltage min 2 V and low-level max 0.8 V.
5 GND power_in Device ground pin.
6 A bidirectional RS-422 or RS-485 data line (driver output and receiver input) with a bus voltage range of -7 V to 12 V and driver output up to ±60 mA.
7 B bidirectional RS-422 or RS-485 data line (driver output and receiver input) with a bus voltage range of -7 V to 12 V and driver output up to ±60 mA.
8 VCC power_in Power input; connect to 5-V power source, recommended range 4.75 V to 5.25 V (absolute maximum 7 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 7 V 4
Voltage range at any bus terminal -10 15 V 4
Enable input voltage VI 5.5 V 4
Operating virtual junction temperature TJ 150 °C 4
Storage temperature range Tstg -65 150 °C 4
Lead temperature 260 °C 1,6 mm (1/16 inch) from case for 10 seconds 4
Supply voltage VCC 4.75 5 5.25 V 4
Voltage at any bus terminal VI or VIC -7 12 V separately or common mode 4
High-level input voltage VIH 2 V D, DE, and RE 4
Low-level input voltage VIL 0.8 V D, DE, and RE 4
Differential input voltage VID -12 12 V 4
High-level output current, driver IOH -60 mA Driver 4
High-level output current, receiver IOH -400 µA Receiver 4
Low-level output current, driver IOL 60 mA Driver 4
Low-level output current, receiver IOL 8 mA Receiver 4
Operating free-air temperature TA 0 70 °C SN75176B 4
Junction-to-ambient thermal resistance RθJA 114.4 °C/W D (SOIC) 8 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 55.1 °C/W D (SOIC) 8 pins 4
Junction-to-board thermal resistance RθJB 61.6 °C/W D (SOIC) 8 pins 4
Junction-to-top characterization parameter ψJT 8.8 °C/W D (SOIC) 8 pins 4
Junction-to-board characterization parameter ψJB 60.8 °C/W D (SOIC) 8 pins 4
Driver input clamp voltage VIK -1.5 V II = -18 mA 5
Driver differential output voltage /VOD2/ 1.5 2.5 5 V RL = 54 Ω, see 图 7-1 5
Driver differential output voltage VOD3 1.5 5 V See (5) 5
Change in magnitude of differential output voltage ∆/VOD/ -0.2 0.2 V RL = 54 Ω or 100 Ω, see 图 7-1 5
Common-mode output voltage VOC -1 3 V RL = 54 Ω or 100 Ω, see 图 7-1 5
Change in magnitude of common-mode output voltage ∆/VOC/ -0.2 0.2 V RL = 54 Ω or 100 Ω, see 图 7-1 5
Output current, output disabled IO 1 mA Output disabled, VO = 12 V 5
Output current, output disabled IO -0.8 mA Output disabled, VO = -7 V 5
Driver high-level input current IIH 20 µA VI = 2.4 V 5
Driver low-level input current IIL -400 µA VI = 0.4 V 5
Driver short-circuit output current IOS -250 mA VO = -7 V 5
Driver short-circuit output current IOS -150 mA VO = 0 5
Driver short-circuit output current IOS 250 mA VO = VCC 5
Supply current (driver table), outputs enabled ICC 42 70 mA No load, outputs enabled 5
Supply current (driver table), outputs disabled ICC 26 35 mA No load, outputs disabled 5
Receiver positive-going input threshold voltage VIT+ 0.2 V VO = 2.7 V, IO = -0.4 mA 6
Receiver negative-going input threshold voltage VIT- -0.2 V VO = 0.5 V, IO = 8 mA 6
Input hysteresis voltage Vhys 50 mV VIT+, VIT- 6
Enable input clamp voltage VIK -1.5 V II = -18 mA 6
Receiver high-level output voltage VOH 2.7 V VID = 200 mV, IOH = -400 µA, see 图 7-2 6
Receiver low-level output voltage VOL 0.45 V VID = -200 mV, IOL = 8 mA, see 图 7-2 6
High-impedance-state output current IOZ -20 20 µA VO = 0.4 V to 2.4 V 6
Line input current II 1 mA Other input = 0 V, VI = 12 V 6
Line input current II -0.8 mA Other input = 0 V, VI = -7 V 6
High-level enable input current IIH 20 µA VIH = 2.7 V 6
Low-level enable input current IIL -100 µA VIL = 0.4 V 6
Input resistance rI 12 kΩ VI = 12 V 6
Receiver short-circuit output current IOS -15 -85 mA 6
Supply current (receiver table), outputs enabled ICC 42 55 mA No load, outputs enabled 6
Supply current (receiver table), outputs disabled ICC 26 35 mA No load, outputs disabled 6
Driver differential-output delay time td(OD) 15 22 ns RL = 54 Ω, see 图 7-3 6
Driver differential-output transition time tt(OD) 20 30 ns RL = 54 Ω, see 图 7-3 6
Driver output enable time to high level tPZH 85 120 ns See 图 7-4 6
Driver output enable time to low level tPZL 40 60 ns See 图 7-5 6
Driver output disable time from high level tPHZ 150 250 ns See 图 7-4 6
Driver output disable time from low level tPLZ 20 30 ns See 图 7-5 6
Receiver propagation delay, low- to high-level output tPLH 21 35 ns VID = 0 to 3 V, see 图 7-6 6
Receiver propagation delay, high- to low-level output tPHL 23 35 ns VID = 0 to 3 V, see 图 7-6 6
Receiver output enable time to high level tPZH 10 20 ns See 图 7-7 6
Receiver output enable time to low level tPZL 12 20 ns See 图 7-7 6
Receiver output disable time from high level tPHZ 20 35 ns See 图 7-7 6
Receiver output disable time from low level tPLZ 17 25 ns See 图 7-7 6

CAD (KiCad official)

  • Symbol: SN75176BD
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sn75176bd-etched.step / sn75176bd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn75176bd.step / sn75176bd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 7a0f14f57c069238, retrieved 2026-10-22, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF