Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN75176B

Texas Instruments · RS-485 / RS-422 transceiver · SOIC-8

A differential bus transceiver for RS-485 and RS-422 multipoint networks, in SOIC-8, the long-time standard part for the job. It pairs one driver and one receiver on the A/B twisted pair, with separate active-high driver-enable (DE) and active-low receiver-enable (/RE) so a node can transmit, receive, or release the bus. It supports up to 32 unit loads on a segment, survives bus contention, and carries data over long cable runs where single-ended signalling fails. Tie DE and /RE together for half-duplex control from one pin. Runs from a single 5 V supply.

Pinout

Pin Name Type Function
1 R output Receiver logic data output. Presents the demodulated single-ended logic level from the differential RS-485 bus (A minus B). High-impedance (tri-state) when RE is deasserted (logic high). VOH ≥ 2.7 V at IOH = -400 µA; VOL ≤ 0.45 V at IOL = 8 mA.
2 RE input Receiver enable, active low. Drive low (VIL ≤ 0.8 V) to enable the receiver output R; drive high (VIH ≥ 2 V) to force R into the high-impedance state. Typically tied to DE (or its inverse) to form a direction-control pin.
3 DE input Driver enable, active high. Drive high (VIH ≥ 2 V) to enable the differential driver onto A/B; drive low (VIL ≤ 0.8 V) to place the driver outputs in the high-impedance state so the bus can be shared by other transceivers.
4 D input Driver logic data input. Single-ended TTL/CMOS-compatible logic level that is transmitted differentially onto the A/B bus lines when DE is asserted high. VIH ≥ 2 V, VIL ≤ 0.8 V.
5 GND power_in Device ground reference. Connect to the system ground plane. All logic-level voltages and the -1 V to +3 V common-mode window on A/B are referenced to this pin.
6 A bidirectional Non-inverting differential bus I/O for RS-422 / RS-485. Driven by the internal driver when DE is high, and monitored by the receiver relative to B. Wide input/output common-mode range and clamp diodes protect against bus faults; short-circuit current is internally limited.
7 B bidirectional Inverting differential bus I/O for RS-422 / RS-485. Driven complementary to A when DE is high; forms the negative side of the differential pair sensed by the receiver. Tolerates -10 V to +15 V at the bus terminal (absolute max).
8 VCC power_in Positive supply input, 5 V nominal (4.75 V to 5.25 V recommended, 7 V absolute max). Bypass with a 0.1 µF ceramic capacitor to GND close to the pin. ICC ≈ 42 mA typ (outputs enabled), 26 mA typ (outputs disabled).

Key specifications

Parameter Value
Type RS-485/RS-422 transceiver
Channels 1 driver + 1 receiver
Bus differential A/B, up to 32 nodes
Enables DE (driver) + /RE (receiver)
Data rate up to 10 Mbps
Fail-safe contention-protected outputs
Supply voltage 5 V
Package SOIC-8

Ordering variants

Same part, different packaging or reel option.

  • SN75176BD (SOIC-8)
  • SN75176BP (PDIP-8)

CAD (KiCad official)

  • Symbol: Interface_UART:SN75176AD (pin-compatible with SN75176B)
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D)
  • 3D model files: sn75176b-etched.step / sn75176b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn75176b.step / sn75176b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 6967824b2ea2d976, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF