# SN75176AP

**Texas Instruments** · Pre-ordered Chips · PDIP-8

SN75176AP from Texas Instruments, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | R | output | Logic data output from the RS-485 receiver; 3-state, high impedance when RE is high, rated for IOH of -400 µA and IOL of 8 mA. |
| 2 | RE | input | Receive enable, active low; a high level puts the receiver output R in high impedance, with VIH min 2 V and VIL max 0.8 V. |
| 3 | DE | input | Driver enable, active high; a low level puts the driver outputs A and B in high impedance, with VIH min 2 V and VIL max 0.8 V. |
| 4 | D | input | Logic data input to the RS-485 driver, with VIH min 2 V and VIL max 0.8 V. |
| 5 | GND | power_in | Device ground pin. |
| 6 | A | bidirectional | RS-422 or RS-485 data line (non-inverting driver output and receiver input), usable over a bus voltage of -7 V to 12 V. |
| 7 | B | bidirectional | RS-422 or RS-485 data line (inverting driver output and receiver input), usable over a bus voltage of -7 V to 12 V. |
| 8 | VCC | power_in | Power input; connect to a 5-V power source (recommended 4.75 V to 5.25 V, absolute max 7 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-8 |
| Category | Interface ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC |  |  | 7 | V |  | 4 |
| Voltage range at any bus terminal |  | -10 |  | 15 | V |  | 4 |
| Enable input voltage | VI |  |  | 5.5 | V |  | 4 |
| Operating free-air temperature range | TA | 0 |  | 70 | °C |  | 4 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 4 |
| Supply Voltage | VCC | 4.75 | 5 | 5.25 | V |  | 4 |
| Voltage at any bus terminal (separately or common mode) | VI or VIC | -7 |  | 12 | V |  | 4 |
| High-level input voltage D, DE, RE | VIH | 2 |  |  | V |  | 4 |
| Low-level input voltage D, DE, RE | VIL |  |  | 0.8 | V |  | 4 |
| Differential input voltage | VID | -12 |  | 12 | V |  | 4 |
| High-level output current, Driver | IOH |  |  | -60 | mA | Driver | 4 |
| High-level output current, Receiver | IOH |  |  | -400 | µA | Receiver | 4 |
| Low-level output current, Driver | IOL |  |  | 60 | mA | Driver | 4 |
| Low-level output current, Receiver | IOL |  |  | 8 | mA | Receiver | 4 |
| Operating free-air temperature | TA | 0 |  | 70 | °C |  | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 66.5 |  | °C/W | P package, 8 pins | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 55.6 |  | °C/W | P package | 4 |
| Junction-to-board thermal resistance | RθJB |  | 42.9 |  | °C/W | P package | 4 |
| Power rating at TA ≤ 25°C |  |  |  | 1100 | mW | P package, TA ≤ 25°C | 4 |
| Power rating at TA = 70°C |  |  |  | 704 | mW | P package, TA = 70°C | 4 |
| Driver input clamp voltage | VIK |  |  | -1.5 | V | II = -18 mA | 5 |
| Driver high-level output voltage | VOH | 3.7 |  |  | V | VIH = 2 V, VIL = 0.8 V, IOH = -33 mA | 5 |
| Driver low-level output voltage | VOL |  |  | 1.1 | V | VIH = 2 V, VIL = 0.8 V, IOH = 33 mA | 5 |
| Differential output voltage | /VOD2/ | 2 |  | 2.7 | V | RL = 100 Ω, see 图 7-1 | 5 |
| Differential output voltage | /VOD2/ | 1.5 |  | 2.4 | V | RL = 54 Ω, see 图 7-1 | 5 |
| Change in magnitude of differential output voltage | Δ/VOD/ | -0.2 |  | 0.2 | V |  | 5 |
| Common-mode output voltage | VOC |  |  | 3 | V | RL = 54 Ω or 100 Ω, see 图 7-1 | 5 |
| Change in magnitude of common-mode output voltage | Δ/VOC/ | -0.2 |  | 0.2 | V |  | 5 |
| Driver output current, output disabled | IO |  |  | 1 | mA | Output disabled, VO = 12 V | 5 |
| Driver output current, output disabled | IO | -0.8 |  |  | mA | Output disabled, VO = -7 V | 5 |
| Driver high-level input current | IIH |  |  | 20 | µA | VI = 2.4 V | 5 |
| Driver low-level input current | IIL | -400 |  |  | µA | VI = 0.4 V | 5 |
| Driver short-circuit output current | IOS | -250 |  |  | mA | VO = -7 V | 5 |
| Driver short-circuit output current | IOS |  |  | 250 | mA | VO = VCC | 5 |
| Driver short-circuit output current | IOS |  |  | 500 | mA | VO = 12 V | 5 |
| Supply current, outputs enabled | ICC |  | 35 | 50 | mA | No load, outputs enabled | 5 |
| Supply current, outputs disabled | ICC |  | 26 | 40 | mA | No load, outputs disabled | 5 |
| Positive-going input threshold voltage | VIT+ |  |  | 0.2 | V | VO = 2.7 V, IO = -0.4 mA | 5 |
| Negative-going input threshold voltage | VIT- | -0.2 |  |  | V | VO = 0.5 V, IO = 8 mA | 5 |
| Input hysteresis voltage | Vhys |  | 50 |  | mV | VIT+, VIT- | 5 |
| Receiver enable clamp voltage | VIK |  |  | -1.5 | V | II = -18 mA | 5 |
| Receiver high-level output voltage | VOH | 2.7 |  |  | V | VID = 200 mV, IOH = -400 µA, See 图 7-2 | 5 |
| Receiver low-level output voltage | VOL |  |  | 0.45 | V | VID = 200 mV, IOH = 8 mA, See 图 7-2 | 5 |
| High-impedance-state output current | IOZ | -20 |  | 20 | µA | VO = 0.4 V to 2.4 V | 5 |
| Line input current | II |  |  | 1 | mA | Other input = 0 V, VI = 12 V | 5 |
| Line input current | II | -0.8 |  |  | mA | Other input = 0 V, VI = -7 V | 5 |
| High-level enable input current | IIH |  |  | 20 | µA | VIH = 2.7 V | 5 |
| Low-level enable input current | IIL | -100 |  |  | µA | VIL = 0.4 V | 5 |
| Input resistance | ri | 12 |  |  | kΩ |  | 5 |
| Receiver short-circuit output current | IOS | -15 |  | -85 | mA |  | 5 |
| Driver differential-output delay time | td(OD) |  | 40 | 60 | ns | RL = 60 Ω, See 图 7-3, VCC = 5 V, TA = 25°C | 6 |
| Driver differential-output transition time | tt(OD) |  | 65 | 95 | ns | RL = 60 Ω, See 图 7-3, VCC = 5 V, TA = 25°C | 6 |
| Driver output enable time to high level | tPZH |  | 55 | 90 | ns | RL = 110 Ω, See 图 7-4 | 6 |
| Driver output enable time to low level | tPZL |  | 30 | 50 | ns | RL = 110 Ω, See 图 7-5 | 6 |
| Driver output disable time from high level | tPHZ |  | 85 | 130 | ns | RL = 110 Ω, See 图 7-4 | 6 |
| Driver output disable time from low level | tPLZ |  | 20 | 40 | ns | RL = 110 Ω, See 图 7-5 | 6 |
| Receiver propagation delay, low-to-high | tPLH |  | 21 | 35 | ns | VID = -1.5 V to 1.5 V, See 图 7-6, CL = 15 pF | 6 |
| Receiver propagation delay, high-to-low | tPHL |  | 23 | 35 | ns | VID = -1.5 V to 1.5 V, See 图 7-6, CL = 15 pF | 6 |
| Receiver output enable time to high level | tPZH |  | 10 | 30 | ns | See 图 7-7, CL = 15 pF | 6 |
| Receiver output enable time to low level | tPZL |  | 12 | 30 | ns | See 图 7-7, CL = 15 pF | 6 |
| Receiver output disable time from high level | tPHZ |  | 20 | 35 | ns | See 图 7-7, CL = 15 pF | 6 |
| Receiver output disable time from low level | tPLZ |  | 17 | 25 | ns | See 图 7-7, CL = 15 pF | 6 |

## CAD (KiCad official)

- Symbol: `SN75176AP`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files: `sn75176ap-etched.step` / `sn75176ap-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn75176ap.step` / `sn75176ap.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn75176ap.pdf) (27 pp, sha256 `2e9e8405f4b2b248`, retrieved 2026-10-27, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn75176ap-datasheet.pdf)