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SN75173N

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Texas Instruments Pre-ordered Chips, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN75173N

Texas Instruments · Pre-ordered Chips · PDIP-16

SN75173N from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1B input Inverting differential line input of receiver 1, with ±200 mV sensitivity over a -12 V to 12 V common-mode range and 12 kΩ min input resistance.
2 1A input Noninverting differential line input of receiver 1, with ±200 mV sensitivity over a -12 V to 12 V common-mode range and 12 kΩ min input resistance.
3 1Y tri_state 3-state output of receiver 1, driven high when inputs are open circuited (fail-safe) and high-impedance when disabled by the enables.
4 G input Active-high enable input shared by all four receivers, ORed with the active-low enable; VIH min 2 V, VIL max 0.8 V.
5 2Y tri_state 3-state output of receiver 2, driven high when inputs are open circuited (fail-safe) and high-impedance when disabled by the enables.
6 2A input Noninverting differential line input of receiver 2, with ±200 mV sensitivity over a -12 V to 12 V common-mode range.
7 2B input Inverting differential line input of receiver 2, with ±200 mV sensitivity over a -12 V to 12 V common-mode range.
8 GND power_in Ground terminal, reference for all voltage values except differential input voltage.
9 3B input Inverting differential line input of receiver 3, with ±200 mV sensitivity over a -12 V to 12 V common-mode range.
10 3A input Noninverting differential line input of receiver 3, with ±200 mV sensitivity over a -12 V to 12 V common-mode range.
11 3Y tri_state 3-state output of receiver 3, driven high when inputs are open circuited (fail-safe) and high-impedance when disabled by the enables.
12 ~{G} input Active-low enable input shared by all four receivers, ORed with the active-high enable; VIH min 2 V, VIL max 0.8 V.
13 4Y tri_state 3-state output of receiver 4, driven high when inputs are open circuited (fail-safe) and high-impedance when disabled by the enables.
14 4A input Noninverting differential line input of receiver 4, with ±200 mV sensitivity over a -12 V to 12 V common-mode range.
15 4B input Inverting differential line input of receiver 4, with ±200 mV sensitivity over a -12 V to 12 V common-mode range.
16 VCC power_in Single 5-V supply; recommended 4.75 V to 5.25 V for SN75173, absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-16
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 7 V see Note 1 4
Input voltage (A or B inputs) VI -25 25 V 4
Differential input voltage VID -25 25 V see Note 2 4
Enable input voltage VI 7 V 4
Low-level output current IOL 50 mA 4
Package thermal impedance, N package θJA 67 °C/W see Note 3, N package 4
Lead temperature, D or N package 260 °C 1,6 mm from case for 10 seconds 4
Storage temperature range Tstg -65 150 °C 4
Supply voltage VCC 4.75 5 5.25 V SN65173, SN75173 4
Common-mode input voltage VIC -12 12 V 4
Differential input voltage VID -12 12 V 4
High-level enable-input voltage VIH 2 V 4
Low-level enable-input voltage VIL 0.8 V 4
High-level output current IOH -400 µA 4
Low-level output current IOL 16 mA 4
Operating free-air temperature TA 0 70 °C SN75173 4
Positive-going input threshold voltage VIT+ 0.2 V VO = 2.7 V, IO = -0.4 mA 5
Negative-going input threshold voltage VIT- -0.2 V VO = 0.5 V, IO = 16 mA 5
Hysteresis (VIT+, VIT-) Vhys 50 mV See Figure 4 5
Enable-input clamp voltage VIK -1.5 V II = -18 mA 5
High-level output voltage VOH 2.7 V VID = 200 mV, IOH = -400 µA, SN75173 5
Low-level output voltage VOL 0.45 V VID = -200 mV, IOL = 8 mA, See Figure 1 5
Low-level output voltage VOL 0.5 V VID = -200 mV, IOL = 16 mA, See Figure 1 5
High-impedance-state output current IOZ -20 20 µA VO = 0.4 V to 2.4 V 5
Line input current II 1 mA Other input at 0 V, VI = 12 V, See Note 3 5
Line input current II -0.8 mA Other input at 0 V, VI = -7 V, See Note 3 5
High-level enable-input current IIH 20 µA VIH = 2.7 V 5
Low-level enable-input current IIL -100 µA VIL = 0.4 V 5
Input resistance ri 12 kΩ 5
Short-circuit output current IOS -15 -85 mA 5
Supply current ICC 70 mA Outputs disabled 5
Propagation delay time, low-to-high-level output tPLH 20 35 ns VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 1, VCC = 5 V, TA = 25°C 5
Propagation delay time, high-to-low-level output tPHL 22 35 ns VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 1, VCC = 5 V, TA = 25°C 5
Output enable time to high level tPZH 17 22 ns CL = 15 pF, See Figure 2 5
Output enable time to low level tPZL 20 25 ns CL = 15 pF, See Figure 3 5
Output disable time from high level tPHZ 21 30 ns CL = 5 pF, See Figure 2 5
Output disable time from low level tPLZ 30 40 ns CL = 5 pF, See Figure 3 5

CAD (KiCad official)

  • Symbol: SN75173N
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: PDIP-16 (KiCad packages3D, STEP)
  • 3D model files: sn75173n-etched.step / sn75173n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn75173n.step / sn75173n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 ea1668424730f0e7, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF