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SN74LVTH573DBR

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Texas Instruments Latches, SSOP-20-5.2mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74LVTH573DBR

Texas Instruments · Latches · SSOP-20-5.2mm

SN74LVTH573DBR from Texas Instruments, in a SSOP-20-5.2mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low buffered output enable: when high, the eight outputs are forced to the high-impedance state, and OE should be tied to VCC through a pullup resistor to keep the outputs in high-impedance during power up and power down.
2 1D input Data input to latch 1 with active bus-hold circuitry that holds the input at a valid logic level when floating; the recommended input voltage maximum is 5.5 V.
3 2D input Data input to latch 2 with active bus-hold circuitry that holds the input at a valid logic level when floating; the recommended input voltage maximum is 5.5 V.
4 3D input Data input to latch 3 with active bus-hold circuitry that holds the input at a valid logic level when floating; the recommended input voltage maximum is 5.5 V.
5 4D input Data input to latch 4 with active bus-hold circuitry that holds the input at a valid logic level when floating; the recommended input voltage maximum is 5.5 V.
6 5D input Data input to latch 5 with active bus-hold circuitry that holds the input at a valid logic level when floating; the recommended input voltage maximum is 5.5 V.
7 6D input Data input to latch 6 with active bus-hold circuitry that holds the input at a valid logic level when floating; the recommended input voltage maximum is 5.5 V.
8 7D input Data input to latch 7 with active bus-hold circuitry that holds the input at a valid logic level when floating; the recommended input voltage maximum is 5.5 V.
9 8D input Data input to latch 8 with active bus-hold circuitry that holds the input at a valid logic level when floating; the recommended input voltage maximum is 5.5 V.
10 GND power_in Device ground reference.
11 LE input Latch enable: while high the Q outputs follow the D inputs, and when taken low the Q outputs latch the levels present at the D inputs, with a minimum high pulse duration of 3 ns.
12 8Q tri_state Three-state output of latch 8 with IOH of -32 mA and IOL of 64 mA maximum for SN74LVTH573 at recommended conditions.
13 7Q tri_state Three-state output of latch 7 with IOH of -32 mA and IOL of 64 mA maximum for SN74LVTH573 at recommended conditions.
14 6Q tri_state Three-state output of latch 6 with IOH of -32 mA and IOL of 64 mA maximum for SN74LVTH573 at recommended conditions.
15 5Q tri_state Three-state output of latch 5 with IOH of -32 mA and IOL of 64 mA maximum for SN74LVTH573 at recommended conditions.
16 4Q tri_state Three-state output of latch 4 with IOH of -32 mA and IOL of 64 mA maximum for SN74LVTH573 at recommended conditions.
17 3Q tri_state Three-state output of latch 3 with IOH of -32 mA and IOL of 64 mA maximum for SN74LVTH573 at recommended conditions.
18 2Q tri_state Three-state output of latch 2 with IOH of -32 mA and IOL of 64 mA maximum for SN74LVTH573 at recommended conditions.
19 1Q tri_state Three-state output of latch 1 with IOH of -32 mA and IOL of 64 mA maximum for SN74LVTH573 at recommended conditions.
20 VCC power_in Supply voltage for SN74LVTH573, specified from 2.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-20-5.2mm
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (recommended) VCC 2.7 3.6 V 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
Input voltage VI 5.5 V 4
High-level output current IOH -32 mA 4
Low-level output current IOL 64 mA 4
Input transition rise or fall rate Δt/Δv 10 ns/V Outputs enabled 4
Power-up ramp rate Δt/ΔVCC 200 μs/V 4
Operating free-air temperature TA -40 85 °C 4
Supply voltage (absolute maximum) VCC -0.5 4.6 V 3
Input voltage range (absolute maximum) VI -0.5 7 V see Note 1 3
Voltage applied to output in high-impedance or power-off state VO -0.5 7 V see Note 1 3
Voltage applied to output in high state VO -0.5 V see Note 1; upper limit printed as VCC + 0.5 V 3
Current into any output in low state (SN74LVTH573) IO 128 mA 3
Current into any output in high state (SN74LVTH573) IO 64 mA see Note 2 3
Input clamp current IIK -50 mA VI < 0 3
Output clamp current IOK -50 mA VO < 0 3
Storage temperature range Tstg -65 150 °C 3
Input clamp voltage VIK -1.2 V VCC = 2.7 V, II = -18 mA 5
High-level output voltage VOH 2.4 V VCC = 2.7 V, IOH = -8 mA 5
High-level output voltage VOH 2 V VCC = 3 V, IOH = -32 mA 5
Low-level output voltage VOL 0.2 V VCC = 2.7 V, IOL = 100 μA 5
Low-level output voltage VOL 0.5 V VCC = 2.7 V, IOL = 24 mA 5
Low-level output voltage VOL 0.4 V VCC = 2.7 V, IOL = 16 mA 5
Low-level output voltage VOL 0.55 V VCC = 3 V, IOL = 64 mA 5
Control inputs input current II 10 μA VCC = 0 or 3.6 V, VI = 5.5 V 5
Control inputs input current II -1 1 μA VCC = 3.6 V, VI = VCC or GND 5
Data inputs input current II 1 μA VCC = 3.6 V, VI = VCC 5
Data inputs input current II -5 μA VCC = 3.6 V, VI = 0 5
Power-off input/output current Ioff -100 100 μA VCC = 0, VI or VO = 0 to 4.5 V 5
Bus-hold current (data inputs) II(hold) 75 μA VCC = 3 V, VI = 0.8 V 5
Bus-hold current (data inputs) II(hold) -75 μA VCC = 3 V, VI = 2 V 5
Bus-hold maximum dynamic current II(hold) -500 500 μA VCC = 3.6 V, VI = 0 to 3.6 V 5
Off-state high-level output current IOZH 5 μA VCC = 3.6 V, VO = 3 V 5
Off-state low-level output current IOZL -5 μA VCC = 3.6 V, VO = 0.5 V 5
Power-up 3-state output current IOZPU -100 100 μA VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care 5
Power-down 3-state output current IOZPD -100 100 μA VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care 5
Supply current, outputs high ICC 0.19 mA VCC = 3.6 V, Outputs high 5
Supply current, outputs low ICC 5 mA VCC = 3.6 V, IO = 0, Outputs low 5
Supply current, outputs disabled ICC 0.19 mA VCC = 3.6 V, VI = VCC or GND, Outputs disabled 5
Increase in supply current per TTL-level input ΔICC 0.2 mA VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND 5
Input capacitance Ci 3 pF VI = 3 V or 0 5
Output capacitance Co 7 pF VO = 3 V or 0 5
Pulse duration, LE high tw 3 ns VCC = 3.3 V ± 0.3 V 6
Setup time, data before LE↓ tsu 0.7 ns VCC = 3.3 V ± 0.3 V 6
Setup time, data before LE↓ tsu 0.6 ns VCC = 2.7 V 6
Hold time, data after LE↓ th 1.5 ns VCC = 3.3 V ± 0.3 V 6
Hold time, data after LE↓ th 1.7 ns VCC = 2.7 V 6
Package thermal impedance, DB package θJA 70 °C/W DB package, per JESD 51-7 3

CAD (KiCad official)

  • Symbol: SN74LVTH573DBR
  • Footprint: Adom_Gen:Texas_Instruments_SN74
  • 3D model: SSOP-20-5.2mm (KiCad packages3D, STEP)
  • 3D model files: sn74lvth573dbr-etched.step / sn74lvth573dbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvth573dbr.step / sn74lvth573dbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 f641d5d3d4b7bb5f, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF