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SN74LVTH540DWR

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, SOIC-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LVTH540DWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-20

SN74LVTH540DWR from Texas Instruments, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Active-low output enable; if either OE1 or OE2 is high, all outputs are forced to the high-impedance state.
2 A1 input Data input for inverting channel 1 with active bus-hold, which holds an unused or undriven input at a valid logic level and should not be combined with external pullup or pulldown resistors.
3 A2 input Data input for inverting channel 2 with active bus-hold, which holds an unused or undriven input at a valid logic level and should not be combined with external pullup or pulldown resistors.
4 A3 input Data input for inverting channel 3 with active bus-hold, which holds an unused or undriven input at a valid logic level and should not be combined with external pullup or pulldown resistors.
5 A4 input Data input for inverting channel 4 with active bus-hold, which holds an unused or undriven input at a valid logic level and should not be combined with external pullup or pulldown resistors.
6 A5 input Data input for inverting channel 5 with active bus-hold, which holds an unused or undriven input at a valid logic level and should not be combined with external pullup or pulldown resistors.
7 A6 input Data input for inverting channel 6 with active bus-hold, which holds an unused or undriven input at a valid logic level and should not be combined with external pullup or pulldown resistors.
8 A7 input Data input for inverting channel 7 with active bus-hold, which holds an unused or undriven input at a valid logic level and should not be combined with external pullup or pulldown resistors.
9 A8 input Data input for inverting channel 8 with active bus-hold, which holds an unused or undriven input at a valid logic level and should not be combined with external pullup or pulldown resistors.
10 GND power_in Ground reference for the device.
11 Y8 tri_state Inverting 3-state output for channel 8 that goes high-impedance when OE1 or OE2 is high, and is rated at IOH of -32 mA and IOL of 64 mA for the SN74LVTH540 at VCC = 3 V.
12 Y7 tri_state Inverting 3-state output for channel 7 that goes high-impedance when OE1 or OE2 is high, and is rated at IOH of -32 mA and IOL of 64 mA for the SN74LVTH540 at VCC = 3 V.
13 Y6 tri_state Inverting 3-state output for channel 6 that goes high-impedance when OE1 or OE2 is high, and is rated at IOH of -32 mA and IOL of 64 mA for the SN74LVTH540 at VCC = 3 V.
14 Y5 tri_state Inverting 3-state output for channel 5 that goes high-impedance when OE1 or OE2 is high, and is rated at IOH of -32 mA and IOL of 64 mA for the SN74LVTH540 at VCC = 3 V.
15 Y4 tri_state Inverting 3-state output for channel 4 that goes high-impedance when OE1 or OE2 is high, and is rated at IOH of -32 mA and IOL of 64 mA for the SN74LVTH540 at VCC = 3 V.
16 Y3 tri_state Inverting 3-state output for channel 3 that goes high-impedance when OE1 or OE2 is high, and is rated at IOH of -32 mA and IOL of 64 mA for the SN74LVTH540 at VCC = 3 V.
17 Y2 tri_state Inverting 3-state output for channel 2 that goes high-impedance when OE1 or OE2 is high, and is rated at IOH of -32 mA and IOL of 64 mA for the SN74LVTH540 at VCC = 3 V.
18 Y1 tri_state Inverting 3-state output for channel 1 that goes high-impedance when OE1 or OE2 is high, and is rated at IOH of -32 mA and IOL of 64 mA for the SN74LVTH540 at VCC = 3 V.
19 OE2 input Active-low output enable; if either OE1 or OE2 is high, all outputs are forced to the high-impedance state.
20 VCC power_in Supply voltage, recommended range 2.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LVTH540DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lvth540dwr-etched.step / sn74lvth540dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvth540dwr.step / sn74lvth540dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 64a818d767ce4d8f, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF