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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74LVTH374DBR

Texas Instruments · Flip Flops · SSOP-20-208mil

SN74LVTH374DBR from Texas Instruments, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Output enable input; when high, places all Q outputs in high-impedance state.
2	1Q	tri_state	Q output of first D-type flip-flop, set on CLK positive edge when OE is low.
3	1D	input	Data input to first flip-flop, sampled on CLK positive edge when OE is low; bus-hold maintains state when undriven.
4	2D	input	Data input to second flip-flop, sampled on CLK positive edge when OE is low; bus-hold maintains state when undriven.
5	2Q	tri_state	Q output of second D-type flip-flop, set on CLK positive edge when OE is low.
6	3Q	tri_state	Q output of third D-type flip-flop, set on CLK positive edge when OE is low.
7	3D	input	Data input to third flip-flop, sampled on CLK positive edge when OE is low; bus-hold maintains state when undriven.
8	4D	input	Data input to fourth flip-flop, sampled on CLK positive edge when OE is low; bus-hold maintains state when undriven.
9	4Q	tri_state	Q output of fourth D-type flip-flop, set on CLK positive edge when OE is low.
10	GND	power_in	Ground reference, 0 V.
11	CLK	input	Clock input, positive edge triggers data input sampling when OE is low.
12	5Q	tri_state	Q output of fifth D-type flip-flop, set on CLK positive edge when OE is low.
13	5D	input	Data input to fifth flip-flop, sampled on CLK positive edge when OE is low; bus-hold maintains state when undriven.
14	6D	input	Data input to sixth flip-flop, sampled on CLK positive edge when OE is low; bus-hold maintains state when undriven.
15	6Q	tri_state	Q output of sixth D-type flip-flop, set on CLK positive edge when OE is low.
16	7Q	tri_state	Q output of seventh D-type flip-flop, set on CLK positive edge when OE is low.
17	7D	input	Data input to seventh flip-flop, sampled on CLK positive edge when OE is low; bus-hold maintains state when undriven.
18	8D	input	Data input to eighth flip-flop, sampled on CLK positive edge when OE is low; bus-hold maintains state when undriven.
19	8Q	tri_state	Q output of eighth D-type flip-flop, set on CLK positive edge when OE is low.
20	VCC	power_in	Positive supply voltage, 2.7 V to 3.6 V recommended operating range.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SSOP-20-208mil
Category	Logic
Pins	20

CAD (KiCad official)

Symbol: SN74LVTH374DBR
Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
3D model: SSOP-20-208mil (KiCad packages3D, STEP)
3D model files: sn74lvth374dbr-etched.step / sn74lvth374dbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvth374dbr.step / sn74lvth374dbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (23 pp, sha256 b137028b3ae5cece, retrieved 2026-09-27, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF