component
SN74LVTH273PWR
Public Made by Adomby adom
Texas Instruments Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"description": "Direct-clear input: when low it forces all Q outputs low regardless of CLK or D (function table, page 2); it is buffered, and CLR high must be set up before CLK↑ per the timing requirements."
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"description": "Individual data input to flip-flop 2; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
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"number": "5",
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"description": "Flip-flop 2 true output, which follows 2D on the positive-going CLK edge and is cleared by CLR low."
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{
"number": "6",
"name": "3Q",
"type": "output",
"description": "Flip-flop 3 true output, which follows 3D on the positive-going CLK edge and is cleared by CLR low."
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"type": "input",
"description": "Individual data input to flip-flop 3; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
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"description": "Individual data input to flip-flop 4; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
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"description": "Individual data input to flip-flop 5; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
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"number": "14",
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"description": "Individual data input to flip-flop 6; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
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"number": "15",
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"description": "Flip-flop 6 true output, which follows 6D on the positive-going CLK edge and is cleared by CLR low."
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"description": "Flip-flop 7 true output, which follows 7D on the positive-going CLK edge and is cleared by CLR low."
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"description": "Individual data input to flip-flop 7; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
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"number": "18",
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"description": "Individual data input to flip-flop 8; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
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{
"number": "19",
"name": "8Q",
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"description": "Flip-flop 8 true output, which follows 8D on the positive-going CLK edge and is cleared by CLR low."
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"number": "20",
"name": "VCC",
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"description": "Supply voltage, 2.7 V to 3.6 V per the recommended operating conditions."
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"name": "Data inputs input current",
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"name": "Power-off input/output current",
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"name": "Bus-hold sustaining current",
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