SN74LVTH273PWR

{
  "slug": "sn74lvth273pwr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "logic ics",
    "sn74lvth273pwr",
    "factory-2.0.0",
    "extractor-text"
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  "dependencies": {},
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    "path": "docs/hero.png"
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    "README.md",
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    "sn74lvth273pwr.kicad_mod",
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    "sn74lvth273pwr.step",
    "sn74lvth273pwr.lbr",
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    "docs/sn74lvth273pwr-datasheet.pdf",
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  "component": {
    "mpn": "SN74LVTH273PWR",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-20",
    "pin_count": 20,
    "category": "Logic ICs",
    "subcategory": "Logic ICs",
    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvth273.pdf",
    "parts": {
      "symbol": "sn74lvth273pwr.kicad_sym",
      "footprint": "sn74lvth273pwr.kicad_mod",
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      "lbr": "sn74lvth273pwr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2876992",
      "digikey": "296-1273-2-ND",
      "mouser": "595-SN74LVTH273PWR"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T06:38:06Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-1273-2-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "595-SN74LVTH273PWR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CLR",
        "type": "input",
        "description": "Direct-clear input: when low it forces all Q outputs low regardless of CLK or D (function table, page 2); it is buffered, and CLR high must be set up before CLK↑ per the timing requirements."
      },
      {
        "number": "2",
        "name": "1Q",
        "type": "output",
        "description": "Flip-flop 1 true output, which follows 1D on the positive-going CLK edge and is cleared by CLR low."
      },
      {
        "number": "3",
        "name": "1D",
        "type": "input",
        "description": "Individual data input to flip-flop 1; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
      },
      {
        "number": "4",
        "name": "2D",
        "type": "input",
        "description": "Individual data input to flip-flop 2; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
      },
      {
        "number": "5",
        "name": "2Q",
        "type": "output",
        "description": "Flip-flop 2 true output, which follows 2D on the positive-going CLK edge and is cleared by CLR low."
      },
      {
        "number": "6",
        "name": "3Q",
        "type": "output",
        "description": "Flip-flop 3 true output, which follows 3D on the positive-going CLK edge and is cleared by CLR low."
      },
      {
        "number": "7",
        "name": "3D",
        "type": "input",
        "description": "Individual data input to flip-flop 3; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
      },
      {
        "number": "8",
        "name": "4D",
        "type": "input",
        "description": "Individual data input to flip-flop 4; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
      },
      {
        "number": "9",
        "name": "4Q",
        "type": "output",
        "description": "Flip-flop 4 true output, which follows 4D on the positive-going CLK edge and is cleared by CLR low."
      },
      {
        "number": "10",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      },
      {
        "number": "11",
        "name": "CLK",
        "type": "input",
        "description": "Buffered positive-edge clock input; data is transferred to the Q outputs on the rising edge, with a maximum clock frequency of 150 MHz and minimum pulse duration of 3.3 ns."
      },
      {
        "number": "12",
        "name": "5Q",
        "type": "output",
        "description": "Flip-flop 5 true output, which follows 5D on the positive-going CLK edge and is cleared by CLR low."
      },
      {
        "number": "13",
        "name": "5D",
        "type": "input",
        "description": "Individual data input to flip-flop 5; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
      },
      {
        "number": "14",
        "name": "6D",
        "type": "input",
        "description": "Individual data input to flip-flop 6; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
      },
      {
        "number": "15",
        "name": "6Q",
        "type": "output",
        "description": "Flip-flop 6 true output, which follows 6D on the positive-going CLK edge and is cleared by CLR low."
      },
      {
        "number": "16",
        "name": "7Q",
        "type": "output",
        "description": "Flip-flop 7 true output, which follows 7D on the positive-going CLK edge and is cleared by CLR low."
      },
      {
        "number": "17",
        "name": "7D",
        "type": "input",
        "description": "Individual data input to flip-flop 7; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
      },
      {
        "number": "18",
        "name": "8D",
        "type": "input",
        "description": "Individual data input to flip-flop 8; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown."
      },
      {
        "number": "19",
        "name": "8Q",
        "type": "output",
        "description": "Flip-flop 8 true output, which follows 8D on the positive-going CLK edge and is cleared by CLR low."
      },
      {
        "number": "20",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage, 2.7 V to 3.6 V per the recommended operating conditions."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The page 1 pin diagram text is scrambled by extraction. GND=10, CLK=11 and VCC=20 are taken from the; The pin numbers for CLR, the D inputs and the Q outputs come from the page 2 logic diagram, where th; The schema has no field for headline electrical specs, so none are reported. The pin descriptions ci"
        ],
        "pages_sent": 22,
        "cost_usd": 0.0873,
        "at": "2026-10-18T06:32:51"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/sn74lvth273.pdf",
        "pages": 22,
        "sha256": "59c245f9eb91b841",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 20,
        "described": 20,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "zmin_mm": -0.0,
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}