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SN74LVTH244APWR

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74LVTH244APWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

SN74LVTH244APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output-enable input for the 1Y outputs; low enables 1Y outputs to follow the 1A inputs, high forces the 1Y outputs to the high-impedance state.
2 1A1 input Data input of buffer channel 1A1; bus-hold circuitry holds this input at its last valid logic level when left floating.
3 2Y4 tri_state 3-state buffer output 2Y4; outputs the logic level of 2A4 when 2OE is low, high-impedance when 2OE is high.
4 1A2 input Data input of buffer channel 1A2; bus-hold circuitry holds this input at its last valid logic level when left floating.
5 2Y3 tri_state 3-state buffer output 2Y3; outputs the logic level of 2A3 when 2OE is low, high-impedance when 2OE is high.
6 1A3 input Data input of buffer channel 1A3; bus-hold circuitry holds this input at its last valid logic level when left floating.
7 2Y2 tri_state 3-state buffer output 2Y2; outputs the logic level of 2A2 when 2OE is low, high-impedance when 2OE is high.
8 1A4 input Data input of buffer channel 1A4; bus-hold circuitry holds this input at its last valid logic level when left floating.
9 2Y1 tri_state 3-state buffer output 2Y1; outputs the logic level of 2A1 when 2OE is low, high-impedance when 2OE is high.
10 GND power_in Ground reference (0 V) for the device.
11 2A1 input Data input of buffer channel 2A1; bus-hold circuitry holds this input at its last valid logic level when left floating.
12 1Y4 tri_state 3-state buffer output 1Y4; outputs the logic level of 1A4 when 1OE is low, high-impedance when 1OE is high.
13 2A2 input Data input of buffer channel 2A2; bus-hold circuitry holds this input at its last valid logic level when left floating.
14 1Y3 tri_state 3-state buffer output 1Y3; outputs the logic level of 1A3 when 1OE is low, high-impedance when 1OE is high.
15 2A3 input Data input of buffer channel 2A3; bus-hold circuitry holds this input at its last valid logic level when left floating.
16 1Y2 tri_state 3-state buffer output 1Y2; outputs the logic level of 1A2 when 1OE is low, high-impedance when 1OE is high.
17 2A4 input Data input of buffer channel 2A4; bus-hold circuitry holds this input at its last valid logic level when left floating.
18 1Y1 tri_state 3-state buffer output 1Y1; outputs the logic level of 1A1 when 1OE is low, high-impedance when 1OE is high.
19 2OE input Active-low output-enable input for the 2Y outputs; low enables 2Y outputs to follow the 2A inputs, high forces the 2Y outputs to the high-impedance state.
20 VCC power_in Supply voltage input; recommended operating range 2.7 V to 3.6 V for the SN74LVTH244A.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LVTH244APWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lvth244apwr-etched.step / sn74lvth244apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvth244apwr.step / sn74lvth244apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 e89cabc8a6867613, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF