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SN74LVTH240PWR

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LVTH240PWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

SN74LVTH240PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output enable for buffer 1; when high, outputs 1Y1 to 1Y4 are in the high-impedance state, and OE should be tied to VCC through a pullup resistor to ensure high-impedance during power up and power down.
2 1A1 input Data input to buffer 1 channel 1, with bus-hold circuitry that holds an unused or undriven input at a valid logic state and a maximum input voltage of 5.5 V.
3 2Y4 tri_state 3-state output of buffer 2 channel 4, which is high impedance when 2OE is high and is disabled by Ioff circuitry during power-down to prevent backflow.
4 1A2 input Data input to buffer 1 channel 2, with bus-hold circuitry that holds an unused or undriven input at a valid logic state and a maximum input voltage of 5.5 V.
5 2Y3 tri_state 3-state output of buffer 2 channel 3, which is high impedance when 2OE is high and is disabled by Ioff circuitry during power-down to prevent backflow.
6 1A3 input Data input to buffer 1 channel 3, with bus-hold circuitry that holds an unused or undriven input at a valid logic state and a maximum input voltage of 5.5 V.
7 2Y2 tri_state 3-state output of buffer 2 channel 2, which is high impedance when 2OE is high and is disabled by Ioff circuitry during power-down to prevent backflow.
8 1A4 input Data input to buffer 1 channel 4, with bus-hold circuitry that holds an unused or undriven input at a valid logic state and a maximum input voltage of 5.5 V.
9 2Y1 tri_state 3-state output of buffer 2 channel 1, which is high impedance when 2OE is high and is disabled by Ioff circuitry during power-down to prevent backflow.
10 GND power_in Ground reference for the device.
11 2A1 input Data input to buffer 2 channel 1, with bus-hold circuitry that holds an unused or undriven input at a valid logic state and a maximum input voltage of 5.5 V.
12 1Y4 tri_state 3-state output of buffer 1 channel 4, which is high impedance when 1OE is high and is disabled by Ioff circuitry during power-down to prevent backflow.
13 2A2 input Data input to buffer 2 channel 2, with bus-hold circuitry that holds an unused or undriven input at a valid logic state and a maximum input voltage of 5.5 V.
14 1Y3 tri_state 3-state output of buffer 1 channel 3, which is high impedance when 1OE is high and is disabled by Ioff circuitry during power-down to prevent backflow.
15 2A3 input Data input to buffer 2 channel 3, with bus-hold circuitry that holds an unused or undriven input at a valid logic state and a maximum input voltage of 5.5 V.
16 1Y2 tri_state 3-state output of buffer 1 channel 2, which is high impedance when 1OE is high and is disabled by Ioff circuitry during power-down to prevent backflow.
17 2A4 input Data input to buffer 2 channel 4, with bus-hold circuitry that holds an unused or undriven input at a valid logic state and a maximum input voltage of 5.5 V.
18 1Y1 tri_state 3-state output of buffer 1 channel 1, which is high impedance when 1OE is high and is disabled by Ioff circuitry during power-down to prevent backflow.
19 2OE input Active-low output enable for buffer 2; when high, outputs 2Y1 to 2Y4 are in the high-impedance state, and OE should be tied to VCC through a pullup resistor to ensure high-impedance during power up and power down.
20 VCC power_in Supply voltage, with a recommended operating range of 2.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LVTH240PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lvth240pwr-etched.step / sn74lvth240pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvth240pwr.step / sn74lvth240pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 fd8c5ff852d83aa5, retrieved 2026-10-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF