component
SN74LVT574PWR
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# SN74LVT574PWR++**Texas Instruments** · Flip Flops · TSSOP-20++SN74LVT574PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Buffered active-low output enable: when high, the eight outputs go to the high-impedance state without affecting the flip-flops, and it should be tied to VCC through a pullup resistor to ensure high impedance during power up or power down. |+| 2 | 1D | input | Data input to flip-flop 1, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating. |+| 3 | 2D | input | Data input to flip-flop 2, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating. |+| 4 | 3D | input | Data input to flip-flop 3, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating. |+| 5 | 4D | input | Data input to flip-flop 4, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating. |+| 6 | 5D | input | Data input to flip-flop 5, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating. |+| 7 | 6D | input | Data input to flip-flop 6, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating. |+| 8 | 7D | input | Data input to flip-flop 7, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating. |+| 9 | 8D | input | Data input to flip-flop 8, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating. |+| 10 | GND | power_in | Ground reference for the device. |+| 11 | CLK | input | Clock input; the Q outputs take the logic levels of the D inputs on the positive clock transition, with clock frequency up to 150 MHz and minimum pulse width of 3.3 ns. |+| 12 | 8Q | tri_state | Three-state output of flip-flop 8, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574. |+| 13 | 7Q | tri_state | Three-state output of flip-flop 7, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574. |+| 14 | 6Q | tri_state | Three-state output of flip-flop 6, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574. |+| 15 | 5Q | tri_state | Three-state output of flip-flop 5, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574. |+| 16 | 4Q | tri_state | Three-state output of flip-flop 4, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574. |+| 17 | 3Q | tri_state | Three-state output of flip-flop 3, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574. |+| 18 | 2Q | tri_state | Three-state output of flip-flop 2, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574. |+| 19 | 1Q | tri_state | Three-state output of flip-flop 1, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574. |+| 20 | VCC | power_in | Supply voltage, recommended 2.7 V to 3.6 V for the SN74LVT574. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-20 |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `SN74LVT574PWR`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)+- 3D model files: `sn74lvt574pwr-etched.step` / `sn74lvt574pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvt574pwr.step` / `sn74lvt574pwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lvt574.pdf) (18 pp, sha256 `5e2b403f93ab6a15`, retrieved 2026-10-07, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvt574pwr-datasheet.pdf)
page.jsonadded+272@@ -0,0 +1,272 @@+{+ "slug": "sn74lvt574pwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74lvt574pwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74lvt574pwr.kicad_sym",+ "sn74lvt574pwr.kicad_mod",+ "sn74lvt574pwr.glb",+ "sn74lvt574pwr.step",+ "sn74lvt574pwr.lbr",+ "docs/hero.png",+ "docs/sn74lvt574pwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74lvt574pwr-hero.glb",+ "sn74lvt574pwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74LVT574PWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-20",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvt574.pdf",+ "parts": {+ "symbol": "sn74lvt574pwr.kicad_sym",+ "footprint": "sn74lvt574pwr.kicad_mod",+ "model_3d": "sn74lvt574pwr-hero.glb",+ "model_3d_plain": "sn74lvt574pwr.glb",+ "model_3d_step": "sn74lvt574pwr-etched.step",+ "model_3d_step_plain": "sn74lvt574pwr.step",+ "lbr": "sn74lvt574pwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2677773",+ "digikey": "296-1257-2-ND",+ "mouser": "595-SN74LVT574PWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T22:27:04Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-1257-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74LVT574PWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "OE",+ "type": "input",+ "description": "Buffered active-low output enable: when high, the eight outputs go to the high-impedance state without affecting the flip-flops, and it should be tied to VCC through a pullup resistor to ensure high impedance during power up or power down."+ },+ {+ "number": "2",+ "name": "1D",+ "type": "input",+ "description": "Data input to flip-flop 1, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating."+ },+ {+ "number": "3",+ "name": "2D",+ "type": "input",+ "description": "Data input to flip-flop 2, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating."+ },+ {+ "number": "4",+ "name": "3D",+ "type": "input",+ "description": "Data input to flip-flop 3, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating."+ },+ {+ "number": "5",+ "name": "4D",+ "type": "input",+ "description": "Data input to flip-flop 4, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating."+ },+ {+ "number": "6",+ "name": "5D",+ "type": "input",+ "description": "Data input to flip-flop 5, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating."+ },+ {+ "number": "7",+ "name": "6D",+ "type": "input",+ "description": "Data input to flip-flop 6, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating."+ },+ {+ "number": "8",+ "name": "7D",+ "type": "input",+ "description": "Data input to flip-flop 7, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating."+ },+ {+ "number": "9",+ "name": "8D",+ "type": "input",+ "description": "Data input to flip-flop 8, sampled on the positive transition of CLK, with active bus-hold circuitry that holds the input at a valid logic level when floating."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "11",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; the Q outputs take the logic levels of the D inputs on the positive clock transition, with clock frequency up to 150 MHz and minimum pulse width of 3.3 ns."+ },+ {+ "number": "12",+ "name": "8Q",+ "type": "tri_state",+ "description": "Three-state output of flip-flop 8, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574."+ },+ {+ "number": "13",+ "name": "7Q",+ "type": "tri_state",+ "description": "Three-state output of flip-flop 7, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574."+ },+ {+ "number": "14",+ "name": "6Q",+ "type": "tri_state",+ "description": "Three-state output of flip-flop 6, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574."+ },+ {+ "number": "15",+ "name": "5Q",+ "type": "tri_state",+ "description": "Three-state output of flip-flop 5, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574."+ },+ {+ "number": "16",+ "name": "4Q",+ "type": "tri_state",+ "description": "Three-state output of flip-flop 4, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574."+ },+ {+ "number": "17",+ "name": "3Q",+ "type": "tri_state",+ "description": "Three-state output of flip-flop 3, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574."+ },+ {+ "number": "18",+ "name": "2Q",+ "type": "tri_state",+ "description": "Three-state output of flip-flop 2, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574."+ },+ {+ "number": "19",+ "name": "1Q",+ "type": "tri_state",+ "description": "Three-state output of flip-flop 1, with recommended IOH of −32 mA and IOL of 64 mA for the SN74LVT574."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, recommended 2.7 V to 3.6 V for the SN74LVT574."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin numbers for OE, 1D–8D, CLK and 1Q–8Q are stated explicitly in the logic symbol on page 2. The pa; The datasheet gives no explicit pin number for GND or VCC. Pins 10 and 20 were assigned from the top; The VCC description uses the recommended supply range from the recommended operating conditions tabl"+ ],+ "pages_sent": 18,+ "cost_usd": 0.0833,+ "at": "2026-10-07T22:26:45"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74lvt574.pdf",+ "pages": 18,+ "sha256": "5e2b403f93ab6a15",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74lvt574pwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "97339947f3a7196470ec2f1d9f9b92bb2fc2ab66ad53be0cf105192585ef3c9a",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74lvt574pwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "c9fcdec5231c67b94af70357b2da2880d048f1144a0774f917652e27970cdd6d",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}