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SN74LVT573PWR
Public Made by Adomby adom
Texas Instruments Latches, SOIC-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74LVT573PWR
Texas Instruments · Latches · SOIC-20
SN74LVT573PWR from Texas Instruments, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low buffered output enable; when high, the eight outputs go to high-impedance, and OE should be tied to VCC through a pullup resistor to keep the outputs high-Z during power-up and power-down. |
| 2 | 1D | input | Data input for latch 1, with active bus-hold so an unused or floating input holds a valid logic level; data is passed to 1Q while LE is high. |
| 3 | 2D | input | Data input for latch 2, with active bus-hold to hold a valid logic level when floating; data is passed to 2Q while LE is high. |
| 4 | 3D | input | Data input for latch 3, with active bus-hold to hold a valid logic level when floating; data is passed to 3Q while LE is high. |
| 5 | 4D | input | Data input for latch 4, with active bus-hold to hold a valid logic level when floating; data is passed to 4Q while LE is high. |
| 6 | 5D | input | Data input for latch 5, with active bus-hold to hold a valid logic level when floating; data is passed to 5Q while LE is high. |
| 7 | 6D | input | Data input for latch 6, with active bus-hold to hold a valid logic level when floating; data is passed to 6Q while LE is high. |
| 8 | 7D | input | Data input for latch 7, with active bus-hold to hold a valid logic level when floating; data is passed to 7Q while LE is high. |
| 9 | 8D | input | Data input for latch 8, with active bus-hold to hold a valid logic level when floating; data is passed to 8Q while LE is high. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | LE | input | Latch enable; while LE is high the Q outputs follow the D inputs, and when LE is taken low the Q outputs latch the levels present at D. |
| 12 | 8Q | tri_state | Output of latch 8, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 13 | 7Q | tri_state | Output of latch 7, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 14 | 6Q | tri_state | Output of latch 6, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 15 | 5Q | tri_state | Output of latch 5, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 16 | 4Q | tri_state | Output of latch 4, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 17 | 3Q | tri_state | Output of latch 3, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 18 | 2Q | tri_state | Output of latch 2, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 19 | 1Q | tri_state | Output of latch 1, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 20 | VCC | power_in | Supply voltage, specified as 2.7 V to 3.6 V for the SN74LVT573. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74LVT573PWR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20 (KiCad packages3D, STEP)
- 3D model files:
sn74lvt573pwr-etched.step/sn74lvt573pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lvt573pwr.step/sn74lvt573pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (17 pp, sha256
4936cbbffffee6ae, retrieved 2026-10-11, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74LVT573PWR
**Texas Instruments** · Latches · SOIC-20
SN74LVT573PWR from Texas Instruments, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low buffered output enable; when high, the eight outputs go to high-impedance, and OE should be tied to VCC through a pullup resistor to keep the outputs high-Z during power-up and power-down. |
| 2 | 1D | input | Data input for latch 1, with active bus-hold so an unused or floating input holds a valid logic level; data is passed to 1Q while LE is high. |
| 3 | 2D | input | Data input for latch 2, with active bus-hold to hold a valid logic level when floating; data is passed to 2Q while LE is high. |
| 4 | 3D | input | Data input for latch 3, with active bus-hold to hold a valid logic level when floating; data is passed to 3Q while LE is high. |
| 5 | 4D | input | Data input for latch 4, with active bus-hold to hold a valid logic level when floating; data is passed to 4Q while LE is high. |
| 6 | 5D | input | Data input for latch 5, with active bus-hold to hold a valid logic level when floating; data is passed to 5Q while LE is high. |
| 7 | 6D | input | Data input for latch 6, with active bus-hold to hold a valid logic level when floating; data is passed to 6Q while LE is high. |
| 8 | 7D | input | Data input for latch 7, with active bus-hold to hold a valid logic level when floating; data is passed to 7Q while LE is high. |
| 9 | 8D | input | Data input for latch 8, with active bus-hold to hold a valid logic level when floating; data is passed to 8Q while LE is high. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | LE | input | Latch enable; while LE is high the Q outputs follow the D inputs, and when LE is taken low the Q outputs latch the levels present at D. |
| 12 | 8Q | tri_state | Output of latch 8, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 13 | 7Q | tri_state | Output of latch 7, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 14 | 6Q | tri_state | Output of latch 6, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 15 | 5Q | tri_state | Output of latch 5, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 16 | 4Q | tri_state | Output of latch 4, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 17 | 3Q | tri_state | Output of latch 3, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 18 | 2Q | tri_state | Output of latch 2, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 19 | 1Q | tri_state | Output of latch 1, which can be placed in high-impedance by OE; the device is rated for IOL of 64 mA and IOH of -32 mA at VCC = 3 V for the SN74LVT573. |
| 20 | VCC | power_in | Supply voltage, specified as 2.7 V to 3.6 V for the SN74LVT573. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20 |
| Category | Logic |
| Pins | 20 |
## CAD (KiCad official)
- Symbol: `SN74LVT573PWR`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20 (KiCad packages3D, STEP)
- 3D model files: `sn74lvt573pwr-etched.step` / `sn74lvt573pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvt573pwr.step` / `sn74lvt573pwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lvt573.pdf) (17 pp, sha256 `4936cbbffffee6ae`, retrieved 2026-10-11, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74lvt573pwr-datasheet.pdf)