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SN74LVCZ245APWR

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LVCZ245APWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

SN74LVCZ245APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIR input Direction-control input: a low level selects B-to-A data transfer and a high level selects A-to-B transfer; it accepts voltages up to 5.5 V.
2 A1 bidirectional A-bus data port 1, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
3 A2 bidirectional A-bus data port 2, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
4 A3 bidirectional A-bus data port 3, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
5 A4 bidirectional A-bus data port 4, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
6 A5 bidirectional A-bus data port 5, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
7 A6 bidirectional A-bus data port 6, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
8 A7 bidirectional A-bus data port 7, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
9 A8 bidirectional A-bus data port 8, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
10 GND power_in Ground reference for the device.
11 B8 bidirectional B-bus data port 8, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
12 B7 bidirectional B-bus data port 7, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
13 B6 bidirectional B-bus data port 6, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
14 B5 bidirectional B-bus data port 5, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
15 B4 bidirectional B-bus data port 4, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
16 B3 bidirectional B-bus data port 3, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
17 B2 bidirectional B-bus data port 2, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
18 B1 bidirectional B-bus data port 1, a 3-state I/O that is high-impedance when OE is high; output current is limited to ±12 mA at 2.7 V and ±24 mA at 3 V.
19 OE input Output-enable input: a low level enables the transceiver and a high level isolates the A and B buses; tie it to VCC through a pullup resistor to hold the high-impedance state above 1.5 V.
20 VCC power_in Supply voltage, 2.7 V to 3.6 V recommended (absolute maximum 6.5 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2.7 3.6 V 3
High-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 3
Low-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 3
Input voltage VI 0 5.5 V 3
Output voltage (high or low state) VO 0 V High or low state 3
Output voltage (3-state) VO 0 5.5 V 3-state 3
High-level output current IOH -12 mA VCC = 2.7 V 3
High-level output current IOH -24 mA VCC = 3 V 3
Low-level output current IOL 12 mA VCC = 2.7 V 3
Low-level output current IOL 24 mA VCC = 3 V 3
Input transition rise or fall rate Δt/Δv 6 ns/V 3
Power-up ramp rate Δt/ΔVCC 150 µs/V 3
Operating free-air temperature TA -40 85 °C 3
Supply voltage range VCC -0.5 6.5 V 2
Input voltage range VI -0.5 6.5 V 2
Voltage applied to output in high-impedance or power-off state VO -0.5 6.5 V High-impedance or power-off state 2
Voltage applied to output in high or low state VO -0.5 V High or low state 2
Input clamp current IIK -50 mA VI < 0 2
Output clamp current IOK -50 mA VO < 0 2
Continuous output current IO -50 50 mA 2
Continuous current through VCC or GND -100 100 mA 2
Package thermal impedance (PW package) θJA 83 °C/W PW package, per JESD 51-7 2
Storage temperature range Tstg -65 150 °C 2
High-level output voltage VOH 2.2 V IOH = -12 mA, VCC = 2.7 V 3
High-level output voltage VOH 2.4 V IOH = -12 mA, VCC = 3 V 3
Low-level output voltage VOL 0.2 V IOL = 100 µA, VCC = 2.7 V to 3.6 V 3
Low-level output voltage VOL 0.4 V IOL = 12 mA, VCC = 2.7 V 3
Low-level output voltage VOL 0.55 V IOL = 24 mA, VCC = 3 V 3
Control input leakage current II -5 5 µA Control inputs VI = 0 to 5.5 V, VCC = 3.6 V 3
Power-off leakage current Ioff -5 5 µA VI or VO = 5.5 V, VCC = 0 3
3-state output leakage current IOZ -5 5 µA VO = 0 to 5.5 V, VCC = 3.6 V 3
Power-up 3-state output current IOZPU -5 5 µA VO = 0.5 V to 2.5 V, OE = don't care, VCC = 0 to 1.5 V 3
Power-down 3-state output current IOZPD -5 5 µA VO = 0.5 V to 2.5 V, OE = don't care, VCC = 1.5 V to 0 3
Quiescent supply current ICC 100 µA VI = VCC or GND, IO = 0, VCC = 3.6 V 3
Additional supply current per input ΔICC 100 µA One input at VCC, 0.6 V, other inputs at VCC or GND, VCC = 2.7 V to 3.6 V 3
Propagation delay (A or B to B or A) tpd 7.3 ns VCC = 2.7 V ± 0.3 V 4
Propagation delay (A or B to B or A) tpd 1.5 6.3 ns VCC = 3.3 V ± 0.3 V 4
Output enable time (OE to A or B) ten 9.5 ns VCC = 2.7 V ± 0.3 V 4
Output enable time (OE to A or B) ten 1.5 8.5 ns VCC = 3.3 V ± 0.3 V 4
Output disable time (OE to A or B) tdis 8.5 ns VCC = 2.7 V ± 0.3 V 4
Output disable time (OE to A or B) tdis 1.7 7.5 ns VCC = 3.3 V ± 0.3 V 4

CAD (KiCad official)

  • Symbol: SN74LVCZ245APWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lvcz245apwr-etched.step / sn74lvcz245apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvcz245apwr.step / sn74lvcz245apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 9865c81acc6a04f4, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF