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SN74LVCH244APWR

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74LVCH244APWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

SN74LVCH244APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input First 4-bit buffer output enable (active low); input accepts 0 to 5.5 V with internal bus-hold.
2 1A1 input First buffer data input bit 1; accepts 0 to 5.5 V with internal bus-hold circuitry.
3 2Y4 tri_state Second buffer tri-state data output bit 4; drives ±50 mA continuous maximum.
4 1A2 input First buffer data input bit 2; accepts 0 to 5.5 V with internal bus-hold circuitry.
5 2Y3 tri_state Second buffer tri-state data output bit 3; drives ±50 mA continuous maximum.
6 1A3 input First buffer data input bit 3; accepts 0 to 5.5 V with internal bus-hold circuitry.
7 2Y2 tri_state Second buffer tri-state data output bit 2; drives ±50 mA continuous maximum.
8 1A4 input First buffer data input bit 4; accepts 0 to 5.5 V with internal bus-hold circuitry.
9 2Y1 tri_state Second buffer tri-state data output bit 1; drives ±50 mA continuous maximum.
10 GND power_in Ground reference (0 V).
11 2A1 input Second buffer data input bit 1; accepts 0 to 5.5 V with internal bus-hold circuitry.
12 1Y4 tri_state First buffer tri-state data output bit 4; drives ±50 mA continuous maximum.
13 2A2 input Second buffer data input bit 2; accepts 0 to 5.5 V with internal bus-hold circuitry.
14 1Y3 tri_state First buffer tri-state data output bit 3; drives ±50 mA continuous maximum.
15 2A3 input Second buffer data input bit 3; accepts 0 to 5.5 V with internal bus-hold circuitry.
16 1Y2 tri_state First buffer tri-state data output bit 2; drives ±50 mA continuous maximum.
17 2A4 input Second buffer data input bit 4; accepts 0 to 5.5 V with internal bus-hold circuitry.
18 1Y1 tri_state First buffer tri-state data output bit 1; drives ±50 mA continuous maximum.
19 2OE input Second 4-bit buffer output enable (active low); input accepts 0 to 5.5 V with internal bus-hold.
20 VCC power_in Supply voltage; 1.65 V to 3.6 V operating range with support for 5 V inputs/outputs in mixed-mode.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LVCH244APWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lvch244apwr-etched.step / sn74lvch244apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvch244apwr.step / sn74lvch244apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 1ffe77489ac0904e, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF