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SN74LVC74AQPWREP

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Texas Instruments Flip Flops, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LVC74AQPWREP

Texas Instruments · Flip Flops · TSSOP-14

SN74LVC74AQPWREP from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLR input Active-low asynchronous clear for flip-flop 1; a low level resets Q low regardless of the other inputs, and the inputs accept up to 5.5 V.
2 1D input Data input for flip-flop 1; with PRE and CLR inactive (high), D meeting the setup and hold times is transferred to the outputs on the positive-going clock edge.
3 1CLK input Positive-edge clock input for flip-flop 1, with a maximum clock frequency of 100 MHz stated for VCC of 2.7 V to 3.6 V.
4 1PRE input Active-low asynchronous preset for flip-flop 1; a low level sets Q high regardless of the other inputs.
5 1Q output True output of flip-flop 1, which takes the level of D on the positive clock edge and is specified for IOH of -24 mA and IOL of 24 mA at VCC = 3 V.
6 1Q̅ output Complementary output of flip-flop 1, the inverse of 1Q, with the same drive limits of -24 mA (IOH) and 24 mA (IOL) at VCC = 3 V.
7 GND power_in Ground reference pin for the device.
8 2Q̅ output Complementary output of flip-flop 2, the inverse of 2Q, with the same drive limits of -24 mA (IOH) and 24 mA (IOL) at VCC = 3 V.
9 2Q output True output of flip-flop 2, which takes the level of D on the positive clock edge and is specified for IOH of -24 mA and IOL of 24 mA at VCC = 3 V.
10 2PRE input Active-low asynchronous preset for flip-flop 2; a low level sets Q high regardless of the other inputs.
11 2CLK input Positive-edge clock input for flip-flop 2, with a maximum clock frequency of 100 MHz stated for VCC of 2.7 V to 3.6 V.
12 2D input Data input for flip-flop 2; with PRE and CLR inactive (high), D meeting the setup and hold times is transferred to the outputs on the positive-going clock edge.
13 2CLR input Active-low asynchronous clear for flip-flop 2; a low level resets Q low regardless of the other inputs, and the inputs accept up to 5.5 V.
14 VCC power_in Positive supply pin; the datasheet specifies operation from 2 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74LVC74AQPWREP
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74lvc74aqpwrep-etched.step / sn74lvc74aqpwrep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc74aqpwrep.step / sn74lvc74aqpwrep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 43b822a559d37a23, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF